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 NameCategoryDevelopment KitFamilyQuartus Prime VersionVendor
AN 680: Product Security Features for Altera Devices - Arria III  Design Example \ Outside Design StoreNon kit specific Arria II Design ExamplesArria II15.1.0 Intel
AN 680: Product Security Features for Altera Devices - Arria V  Design Example \ Outside Design StoreNon kit specific Arria V Design ExamplesArria V15.1.0 Intel
AN 680: Product Security Features for Altera Devices - Arria V  Design Example \ Outside Design StoreNon kit specific Arria V Design ExamplesArria V16.0.0 Intel
AN 680: Product Security Features for Altera Devices - Stratix V  Design Example \ Outside Design StoreNon kit specific Stratix V Design ExamplesStratix V15.1.0 Intel
AN 680: Product Security Features for Altera Devices - Stratix V  Design Example \ Outside Design StoreNon kit specific Stratix V Design ExamplesStratix V16.0.0 Intel
AN 684: Design Guidelines for 100 Gbps  Design Example \ Outside Design StoreStratix V GT Transceiver Signal Integrity Development KitStratix V14.0.0 Intel
AN 690: PCI Express DMA Reference Design for Stratix V Devices  Design Example \ Outside Design StoreStratix V GX FPGA Development Kit Stratix V14.0.0 Intel
AN 696: Using the JESD204B MegaCore Function in Arria V Devices  Design Example \ Outside Design StoreArria V GT Development KitArria V15.0.0 Intel
AN 697: Implementing Audio IP in SDI II on Arria V Development Board  Design Example \ Outside Design StoreArria V GX Starter KitArria V14.0.0 Intel
AN 701: Scalable Low Latency Ethernet 10G MAC using Arria 10 1G/10G PHY  Design Example \ Outside Design StoreNon kit specific Arria 10 Design ExamplesArria 1015.0.0 Intel
AN 702: Interfacing a USB PHY to the Hard Processor System USB 2.0 OTG Controller for Arria V  Design Example \ Outside Design StoreNon kit specific Arria V Design ExamplesArria V14.0.0 Intel
AN 702: Interfacing a USB PHY to the Hard Processor System USB 2.0 OTG Controller for Cyclone V  Design Example \ Outside Design StoreNon kit specific Cyclone V Design ExamplesCyclone V14.0.0 Intel
AN 705: Scalable 10G Ethernet MAC using 1G/10G PHY  Design Example \ Outside Design StoreStratix V GX Transceiver Signal Integrity Development KitStratix V15.0.0 Intel
AN 706: Mapping HPS IP Peripheral Signals to the FPGA Interface  Design Example \ Outside Design StoreCyclone V SoC Development KitCyclone V14.0.0 Intel
AN 708: PCI Express DMA Reference Design Using External DDR3 Memory for Arria V GZ  Design Example \ Outside Design StoreArria V GZ Development KitArria V14.0.0 Intel
AN 708: PCI Express DMA Reference Design Using External DDR3 Memory for Stratix V  Design Example \ Outside Design StoreStratix V GX FPGA Development Kit Stratix V14.0.0 Intel
AN 709: HPS SoC Boot Guide - Cyclone V SoC Development Kit  Design Example \ Outside Design StoreCyclone V SoC Development KitCyclone V15.0.0 Intel
AN 717: Nios II Gen2 Hardware Development Tutorial for Arria V  Design Example \ Outside Design StoreNon kit specific Arria V Design ExamplesArria V14.0.0 Intel
AN 717: Nios II Gen2 Hardware Development Tutorial for Cyclone V  Design Example \ Outside Design StoreNon kit specific Cyclone V Design ExamplesCyclone V14.0.0 Intel
AN 717: Nios II Gen2 Hardware Development Tutorial for MAX 10 NEEK  Design Example \ Outside Design StoreMAX 10 NEEKMAX 1014.0.0 Intel