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 NameCategoryDevelopment KitFamilyQuartus Prime VersionVendor
  Stratix 10 IOPLL Dynamic Phase Shift  Design ExampleStratix 10 GX FPGA Development KitStratix 1017.1.0 ProIntel
  Stratix 10 IOPLL Reconfiguration Clock Gating  Design ExampleStratix 10 GX FPGA Development KitStratix 1017.1.0 ProIntel
  Stratix 10 IOPLL Reconfiguration Dynamic Phase Shift  Design ExampleStratix 10 GX FPGA Development KitStratix 1017.1.0 ProIntel
  Stratix 10 IOPLL Reconfiguration MIF Streaming  Design ExampleStratix 10 GX FPGA Development KitStratix 1017.1.0 ProIntel
  Stratix 10 Mailbox Client Intel FPGA IP Core Design Example(QSPI flash Access and Remote System Update)  Design ExampleStratix 10 GX L-Tile Development KitStratix 1020.4.0 ProIntel
  Stratix 10 PAC 4 Channel DDR4 RDIMM  Design ExampleStratix 10 GX FPGA Development KitStratix 1018.1.0 ProIntel
  Stratix 10 PCIe Gen3 x8 DMA  Design ExampleStratix 10 GX L-Tile Development KitStratix 1018.0.0 ProIntel
  Stratix 10 Serial Flash Mailbox Client Intel FPGA IP Core Design Example  Design ExampleStratix 10 GX FPGA Development KitStratix 1018.0.0 ProIntel
  Stratix 10 TX PAM4 8 x 51Gbps with QSFPDD 1x1 Interface Design Example 18.1  Design ExampleStratix 10 Transceiver Signal Integrity Development KitStratix 1018.1.0 ProIntel
  Stratix® 10 TX NRZ 16 x 28Gbps with QSFPDD 1x2 Interface Design Example 18.1   Design ExampleStratix 10 Transceiver Signal Integrity Development KitStratix 1018.1.0 ProIntel
  Stratix® 10 TX NRZ 16 x 28Gbps with QSFPDD 2x1 Interface Design Example 18.1  Design ExampleStratix 10 Transceiver Signal Integrity Development KitStratix 1018.1.0 ProIntel
  Stratix® 10 TX PAM4 2 x 51Gbps with SMA Design Example 18.1  Design ExampleStratix 10 Transceiver Signal Integrity Development KitStratix 1018.1.0 ProIntel
  Ultra Low Latency Ethernet 10G Reference Design for Intel® Stratix® 10 Devices  Design ExampleStratix 10 Transceiver Signal Integrity Development KitStratix 1018.0.0 ProIntel