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 NameCategoryDevelopment KitFamilyQuartus Prime VersionVendor
Implementing OFDM Modulation and Demodulation  Design Example \ Outside Design StoreNon kit specific Stratix V Design ExamplesStratix V7.2 Intel
JPEG Decoder Design Example (OpenCL)  Design Example \ Outside Design StoreNon kit specific Stratix V Design ExamplesStratix V15.1.0 Intel
JPEG Decoder Design Example (OpenCL)  Design Example \ Outside Design StoreNon kit specific Stratix V Design ExamplesStratix V16.0.0 Intel
100Gbps Ethernet 10x10 MAC PHY IP CFP Hardware Demo Design  Design Example \ Outside Design StoreStratix V GX 100G Development KitStratix V15.0 Intel
100Gbps Ethernet CAUI-4 CFP2 Hardware Demo Design  Design Example \ Outside Design StoreStratix V GX 100G Development KitStratix V13.0 Intel
100Gbps Ethernet PHY only Testbench  Design Example \ Outside Design StoreNon kit specific Stratix V Design ExamplesStratix V16.0.2 Intel
40G Base-KR4 Ethernet Hardware Demo  Design Example \ Outside Design StoreStratix V GT Transceiver Signal Integrity Development KitStratix V13.1 Intel
  40Gbps Ethernet MACPHY IP Hardware Demo Design using QSFP   Design ExampleStratix V GX FPGA Development Kit Stratix V17.1.0 StandardIntel
40Gbps Ethernet MACPHY IP Pause Control Demo Design  Design Example \ Outside Design StoreStratix V GX 100G Development KitStratix V13.0 Intel
40Gbps Ethernet MACPHY IP Reference Design  Design Example \ Outside Design StoreStratix V GX 100G Development KitStratix V12.1 Intel
Altera Triple-Speed Ethernet Timing Contraints Design Example (Multi-core)  Design Example \ Outside Design StoreNon kit specific Stratix V Design ExamplesStratix V12.0 Intel
AN 307: Altera Design Flow for Xilinx Users  Design Example \ Outside Design StoreNon kit specific Stratix V Design ExamplesStratix V12.1 Intel
AN 456: PCI Express High Performance Reference Design for Stratix V FPGA  Design Example \ Outside Design StoreNon kit specific Stratix V Design ExamplesStratix V14.0.0 Intel
AN 518: SGMII Interface Implementation Using Soft-CDR Mode of Altera FPGAs - Stratix V  Design Example \ Outside Design StoreNon kit specific Stratix V Design ExamplesStratix V13.0 Intel
AN 522: Implementing Bus LVDS Interface in Supported Altera Device Families - Stratix V  Design Example \ Outside Design StoreNon kit specific Stratix V Design ExamplesStratix V15.0.0 Intel
AN 680: Product Security Features for Altera Devices - Stratix V  Design Example \ Outside Design StoreNon kit specific Stratix V Design ExamplesStratix V15.1.0 Intel
AN 680: Product Security Features for Altera Devices - Stratix V  Design Example \ Outside Design StoreNon kit specific Stratix V Design ExamplesStratix V16.0.0 Intel
AN 684: Design Guidelines for 100 Gbps  Design Example \ Outside Design StoreStratix V GT Transceiver Signal Integrity Development KitStratix V14.0.0 Intel
AN 690: PCI Express DMA Reference Design for Stratix V Devices  Design Example \ Outside Design StoreStratix V GX FPGA Development Kit Stratix V14.0.0 Intel
AN 705: Scalable 10G Ethernet MAC using 1G/10G PHY  Design Example \ Outside Design StoreStratix V GX Transceiver Signal Integrity Development KitStratix V15.0.0 Intel