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 NameCategoryDevelopment KitFamilyQuartus Prime VersionVendor
  1G/2.5G Ethernet Design Example for Intel Stratix 10 Devices  Design ExampleStratix 10 Transceiver Signal Integrity Development KitStratix 1017.1.0 ProIntel
  AN 830: Intel FPGA Triple-Speed Ethernet and On-Board PHY Chip Reference Design for Intel Stratix 10 Devices  Design ExampleStratix 10 GX FPGA Development KitStratix 1020.4.0 ProIntel
  AN 888: PHY Lite for Parallel Interface Reference Design with Dynamic Reconfiguration for Intel® Stratix® 10 Devices  Design ExampleStratix 10 GX FPGA Development KitStratix 1019.1.0 ProIntel
  AN804: Implementing Synchronized ADC-Stratix 10 Multi-Link Design with JESD204B RX IP Core  Design ExampleNon kit specific Stratix 10 Design ExampleStratix 1017.1.0 ProIntel
  AN804: Implementing Unsynchronized ADC-Stratix 10 Multi-Link Design with JESD204B RX IP Core  Design ExampleNon kit specific Stratix 10 Design ExampleStratix 1017.1.0 ProIntel
  AN881: PCIe Gen3x16 Avalon-MM DMA with DDR4 and HBM2 Reference Design  Design ExampleStratix 10 MX FPGA Development KitStratix 1019.2.0 ProIntel
  FIFO V FIFO2 Simulation  Design ExampleStratix 10 GX FPGA Development KitStratix 1018.0.0 ProIntel
  FIFO V FIFO2 Simulation  Design ExampleStratix 10 GX FPGA Development KitStratix 1018.1.0 ProIntel
  Intel® Stratix 10® GX 16-Lane RX JESD204B-ADC12DJ3200 Interoperability Reference Design   Design ExampleStratix 10 Transceiver Signal Integrity Development KitStratix 1017.1.0 ProIntel
  Intel® Stratix® 10 H-tile CvP Example Design for Initialization mode  Design ExampleStratix 10 GX FPGA Development KitStratix 1019.3.0 ProIntel
  Intel® Stratix® 10 H-tile CvP Example Design for Update mode  Design ExampleStratix 10 GX FPGA Development KitStratix 1019.3.0 ProIntel
  ODI eye scan using NIOS II  Design ExampleNon kit specific Stratix 10 Design ExampleStratix 1018.1.1 ProIntel
  PCI Express Gen3 x16 AVMM DMA with DDR4 Memory Reference Design  Design ExampleStratix 10 MX FPGA Development KitStratix 1018.1.0 ProIntel
  PCI Express Gen3 x16 AVMM DMA with HBM2 Memory Reference Design  Design ExampleStratix 10 MX FPGA Development KitStratix 1018.1.0 ProIntel
  PCI Express Gen3 x16 AVMM DMA with On-Chip Memory Reference Design  Design ExampleStratix 10 MX FPGA Development KitStratix 1018.1.0 ProIntel
  RapidIO II Reference Design for Avalon-ST Pass-Through Interface  Development KitStratix 10 GX L-Tile Development KitStratix 1017.1.0 ProIntel
  Stratix 10 CvP Initialization Example Design  Design ExampleStratix 10 GX FPGA Development KitStratix 1017.1.0 ProIntel
  Stratix 10 H-tile CvP design example  Design ExampleStratix 10 GX FPGA Development KitStratix 1017.1.0 ProIntel
  Stratix 10 H-Tile Multi-loopback modes Simulation Reference Design  Design ExampleNon kit specific Stratix 10 Design ExampleStratix 1017.0ir4.0 StandardIntel
  Stratix 10 IOPLL Advanced Mode Reconfiguration   Design ExampleStratix 10 GX FPGA Development KitStratix 1018.1.0 ProIntel Public Cloud