Design Store

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 NameCategoryDevelopment KitFamilyQuartus Prime VersionVendorDownloads
  Accelerated Nios II/e Embedded System  Design ExampleCyclone 10 LP FPGA Evaluation KitCyclone 10 LP17.0.0 StandardSynaptic Laboratories Ltd.56
  Adapting Digilent PmodCLP LCD to Cyclone 10 LP Development Kit with switches, push buttons, LEDs and “Hello C10LP” Display  Design ExampleCyclone 10 LP FPGA Evaluation KitCyclone 10 LP17.0.0 StandardIntel84
  Avalon Verification IP Suite(Single Avalon-MM Master and Slave Pair)  Design ExampleCyclone 10 LP FPGA Evaluation KitCyclone 10 LP17.0.0 StandardIntel25
  Avalon Verification IP Suite(Two Avalon-MM Master and Slave Pair)  Design ExampleCyclone 10 LP FPGA Evaluation KitCyclone 10 LP17.0.0 StandardIntel20
  Boot from EPCQ (Serial Flash) example  Design ExampleCyclone 10 LP FPGA Evaluation KitCyclone 10 LP17.0.0 StandardSynaptic Laboratories Ltd.111
  Boot from EPCQ (Serial Flash) example  Design ExampleCyclone 10 LP FPGA Evaluation KitCyclone 10 LP17.1.0 StandardSynaptic Laboratories Ltd.50
Build a Custom Hardware System  Design Example \ Outside Design StoreCyclone 10 LP FPGA Evaluation KitCyclone 10 LP17.0.0 StandardIntel141
  Crosspoint Switch Matrices in Cyclone 10 LP devices (AN 294 - custom example)   Design ExampleNon kit specific Cyclone 10 LP Design ExamplesCyclone 10 LP17.0.0 StandardIntel16
  Custom Instruction and Nios II Processor  Design ExampleCyclone 10 LP FPGA Evaluation KitCyclone 10 LP17.0.0 StandardIntel38
  Custom Instruction for Nios II Processor for Cyclone 10  Design ExampleCyclone 10 LP FPGA Evaluation KitCyclone 10 LP17.0.0 StandardIntel49
  Cyclone 10 LP FPGA Evaluation Kit Baseline Pinout  Design ExampleCyclone 10 LP FPGA Evaluation KitCyclone 10 LP17.0.0 StandardIntel141
  Cyclone 10 LP Multiprocessor Nios II System Reference Design  Design ExampleCyclone 10 LP FPGA Evaluation KitCyclone 10 LP17.0.0 StandardIntel54
  Cyclone 10 LP Nios II 'Hello World' Design  Design ExampleCyclone 10 LP FPGA Evaluation KitCyclone 10 LP17.0.0 StandardIntel154
  Cyclone 10 LP Nios II 'Hello World' Design  Design ExampleCyclone 10 LP FPGA Evaluation KitCyclone 10 LP17.1std.1 StandardIntel85
  Cyclone 10 LP Nios II Hardware Development Reference Design   Design ExampleCyclone 10 LP FPGA Evaluation KitCyclone 10 LP17.0.0 StandardIntel119
  Cyclone 10 LP PWM Reference Design  Design ExampleCyclone 10 LP FPGA Evaluation KitCyclone 10 LP17.0.0 StandardIntel85
  Cyclone 10 LP Remote System Update Design Example  Design ExampleCyclone 10 LP FPGA Evaluation KitCyclone 10 LP17.0.0 StandardIntel185
  Cyclone 10 LP SPI Slave to Avalon Master Bridge Design Example  Design ExampleCyclone 10 LP FPGA Evaluation KitCyclone 10 LP17.0.0 StandardIntel62
Debug FPGA Hardware with System Console  Design Example \ Outside Design StoreCyclone 10 LP FPGA Evaluation KitCyclone 10 LP17.0.0 StandardIntel62
  Dual Core Nios II Project with protected memory regions  Design ExampleCyclone 10 LP FPGA Evaluation KitCyclone 10 LP17.0.0 StandardSynaptic Laboratories Ltd.27