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 NameCategoryDevelopment KitFamilyQuartus Prime VersionVendor
1G/2.5G Ethernet Design Example for Arria V Devices  Design Example \ Outside Design StoreArria V GT Development KitArria V15.1 Intel
AN 307: Altera Design Flow for Xilinx Users - Arria V  Design Example \ Outside Design StoreNon kit specific Arria V Design ExamplesArria V12.1 Intel
AN 456: PCI Express High Performance Reference Design  Design Example \ Outside Design StoreNon kit specific Arria V Design ExamplesArria V14.0.0 Intel
AN 518: SGMII Interface Implementation Using Soft-CDR Mode of Altera FPGAs  Design Example \ Outside Design StoreNon kit specific Arria V Design ExamplesArria V13.0 Intel
AN 522: Implementing Bus LVDS Interface in Supported Altera Device Families - Arria V  Design Example \ Outside Design StoreNon kit specific Arria V Design ExamplesArria V15.0.0 Intel
AN 676: Using the Transceiver Reconfiguration Controller for Dynamic Reconfiguration in Arria V and Cyclone V Devices - Arria V  Design Example \ Outside Design StoreNon kit specific Arria V Design ExamplesArria V15.0.0 Intel
AN 680: Product Security Features for Altera Devices - Arria V  Design Example \ Outside Design StoreNon kit specific Arria V Design ExamplesArria V15.1.0 Intel
AN 680: Product Security Features for Altera Devices - Arria V  Design Example \ Outside Design StoreNon kit specific Arria V Design ExamplesArria V16.0.0 Intel
AN 696: Using the JESD204B MegaCore Function in Arria V Devices  Design Example \ Outside Design StoreArria V GT Development KitArria V15.0.0 Intel
AN 697: Implementing Audio IP in SDI II on Arria V Development Board  Design Example \ Outside Design StoreArria V GX Starter KitArria V14.0.0 Intel
AN 702: Interfacing a USB PHY to the Hard Processor System USB 2.0 OTG Controller for Arria V  Design Example \ Outside Design StoreNon kit specific Arria V Design ExamplesArria V14.0.0 Intel
AN 708: PCI Express DMA Reference Design Using External DDR3 Memory for Arria V GZ  Design Example \ Outside Design StoreArria V GZ Development KitArria V14.0.0 Intel
AN 717: Nios II Gen2 Hardware Development Tutorial for Arria V  Design Example \ Outside Design StoreNon kit specific Arria V Design ExamplesArria V14.0.0 Intel
AN 720: Simulating the ASMI Block in Your Design  Design Example \ Outside Design StoreNon kit specific Arria V Design ExamplesArria V14.0.0 Intel
AN 720: Simulating the ASMI Block in Your Design for Arria V GZ Device  Design Example \ Outside Design StoreArria V GZ Development KitArria V14.0.0 Intel
AN 756: Altera GPIO to Altera PHYLite Design Implementing Guidelines  Design Example \ Outside Design StoreArria V SoC Development KitArria V15.0.0 Intel
AN647: Single-Port Triple-Speed Ethernet and On-Board PHY Chip Reference Design - Arria V  Design Example \ Outside Design StoreArria V GX Starter KitArria V15.0.0 Intel
AN653: Implementing the CPRI Protocol using the Deterministic Latency Transceiver PHY IP Core - Arria V  Design Example \ Outside Design StoreNon kit specific Arria V Design ExamplesArria V13.0 Intel
AN661: Implementing Fractional PLL Reconfiguration with Altera PLL and Altera PLL Reconfig Megafunctions - Arria V  Design Example \ Outside Design StoreNon kit specific Arria V Design ExamplesArria V15.0.0 Intel
AN739 Altera 1588 System Solution  Design Example \ Outside Design StoreArria V SoC Development KitArria V15.0.0 Intel