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 NameCategoryDevelopment KitFamilyQuartus Prime VersionVendor
  Agilex I/O PLL Reconfiguration  Design ExampleAgilex F-Series Transceiver-SoC Development KitAgilex19.4.0 ProIntel
  Agilex Mailbox Client Intel FPGA IP Core Design Example(QSPI flash Access and Remote System Update)  Design ExampleAgilex F-Series Transceiver-SoC Development KitAgilex19.3.0 ProIntel
  AN901: Implementing Synchronized ADC-Agilex E-Tile Dual Link Design with JESD204C RX IP Core  Design ExampleAgilex F-Series Transceiver-SoC Development KitAgilex20.1.0 ProIntel
  Chip ID Reading using AVST Mailbox IP in Agilex  Design ExampleAgilex F-Series Transceiver-SoC Development KitAgilex19.3.0 ProIntel
  Design Example: Achieving Timing Closure When Using Top I/O Sub Bank in Intel Agilex Devices  Design ExampleNon kit specific Agilex F-Series Design ExampleAgilex20.3.0 ProIntel
  Intel Agilex P-tile CvP Example Design for Initialization mode  Design ExampleAgilex F-Series FPGA Development KitAgilex20.1.0 ProIntel
  Intel FPGA Triple-Speed Ethernet and On-Board PHY Chip Reference Design for Agilex™ Devices  Design ExampleAgilex F-Series Transceiver-SoC Development KitAgilex20.2.0 ProIntel