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Accelerated FIR with Built-In Direct Memory Access Example, Nios II Embedded Evaluation Kit Edition  


CategoryDesign Example \ Outside Design Store
Name Accelerated FIR with Built-In Direct Memory Access Example, Nios II Embedded Evaluation Kit Edition
DescriptionThe finite impulse response (FIR) filter is a common algorithm used in digital signal processing (DSP) systems. In this example, a FIR filter has been integrated into a single SOPC Builder component containing Avalon® Memory-Mapped (Avalon-MM) read and write masters. The read master is responsible for supplying the filter with input data, while the write master is responsible for writing the filter response back to memory. Since the filter has Avalon mastering capabilities, you do not need to use a separate direct memory access (DMA) engine to accomplish the filter operation.
Operating SystemNone
IP Core
IP CoreHeading
Version1.0
FamilyCyclone III
DeviceEP3C25
Documentation
DocumentDescription
Accelerated FIR with Built-In Direct Memory Access Example-
Development KitNios II Embedded Evaluation Kit (NEEK), Cyclone III Edition
Quartus Prime VersionDownload Quartus Prime v9.0
Quartus Prime EditionStandard
VendorIntel


Last updated on March 7, 2017, 4:23 p.m.