Design Store


Avalon Memory-Mapped Master Templates  


CategoryDesign Example \ Outside Design Store
Name Avalon Memory-Mapped Master Templates
DescriptionThe templates provided contain Avalon® Memory-Mapped (MM) Verilog modules bundled as an SOPC Builder-ready component. The component is capable of accessing memory and exposes a simple interface you can access with your own custom logic. The component is parameterizable, allowing you to trade off functionality for area and performance optimizations. You can use the components with any Altera® device family supported by SOPC Builder. The component is Verilog based, so you can add your own custom logic to create a self-contained component. Simply use the component editor available in SOPC Builder to create a new component based on the master template Verilog file and your own source file(s). For ease of use, the component uses Tcl callbacks to allow you to make setting changes automatically in a GUI environment.
Operating SystemNone
IP Core
IP CoreHeading
Version1.0
FamilyStratix IV
DeviceEP4S100G2ES
Documentation
DocumentDescription
Avalon Memory-Mapped Master Templates-
Development KitNon Kit Specific Stratix IV Design Examples
Quartus Prime VersionDownload Quartus Prime v8.0
Quartus Prime EditionStandard
VendorIntel


Last updated on Feb. 26, 2016, 11:45 a.m.