|Name||Design Example: Achieving Timing Closure When Using Top I/O Sub Bank in Intel Agilex Devices|
|Description||This application note describes two methods to resolve these timing violations using|
the GPIO Intel FPGA IP. The analysis in this document focuses on the input data paths
from the GPIO Intel FPGA IP to the FPGA core.There are 3 project revisions for this application note:
• top – original design example with setup timing violation.
• top_w1 – design example using negative edge clock latching solution.
• top_w2 – design example using half-rate transfer mode solution.
|Development Kit||Non kit specific Agilex F-Series Design Example|
Download (The download link will expire on Oct. 22, 2021, 12:55 a.m., please refresh the page to get a new link.)
Note: After downloading the design example, you must prepare the design template. The file you downloaded is of the form of a <project>.par file which contains a compressed version of your design files (similar to a .qar file) and metadata describing the project. The combination of this information is what constitutes a <project>.par file. In releases 16.0 or newer, you can simply double click on the <project>.par file and Quartus will launch that project.
Browse to the <project>.par file you downloaded, click next, followed by Finish, and your design template will be installed and displayed in the Project Navigator pane in Quartus.
Note: When a design is stored in the Design Store as a design template, it has been previously regression tested against the stated version of Quartus software. The regression ensures the design template passes analysis/synthesis/fitting/assembly steps in the Quartus design flow.
At the command-line, type the following command:
Once the process completes, then type:
|Quartus Prime Version||Download Quartus Prime v20.3|
|Quartus Prime Edition||Pro|
Last updated on Dec. 3, 2020, 8:02 p.m.