Design Store


Design Example: Achieving Timing Closure When Using Top I/O Sub Bank in Intel Agilex Devices  


CategoryDesign Example
NameDesign Example: Achieving Timing Closure When Using Top I/O Sub Bank in Intel Agilex Devices
DescriptionThis application note describes two methods to resolve these timing violations using
the GPIO Intel FPGA IP. The analysis in this document focuses on the input data paths
from the GPIO Intel FPGA IP to the FPGA core.There are 3 project revisions for this application note:
• top – original design example with setup timing violation.
• top_w1 – design example using negative edge clock latching solution.
• top_w2 – design example using half-rate transfer mode solution.
Operating SystemNone
IP Core
IP CoreHeading
Altera GPIOOther
Altera IOPLLClocksPLLsResets
Version1.0
FamilyAgilex
DeviceAGFA014_R0
Documentation
DocumentDescription
AN911 Achieving Timing Closure When Using Top I/O Sub Bank in Intel Agilex DevicesThis application note describes two methods to resolve these timing violations using the GPIO Intel FPGA IP. The analysis in this document focuses on the input data paths from the GPIO Intel FPGA IP to the FPGA core.
Design Example:Achieving Timing Closure When Using Top I/O Sub Bank in Intel Agilex Devices Design ExampleThis FPGA wiki is created to describes the design examples that exemplifies the setup timing violation that occurs when using the top I/O sub-bank for GPIO applications and two methods to resolve this timing violation using the GPIO Intel FPGA IP
Development KitNon kit specific Agilex F-Series Design Example
Installation Package

Note: After downloading the design example, you must prepare the design template. The file you downloaded is of the form of a <project>.par file which contains a compressed version of your design files (similar to a .qar file) and metadata describing the project. The combination of this information is what constitutes a <project>.par file. In releases 16.0 or newer, you can simply double click on the <project>.par file and Quartus will launch that project.

The second means to bring up the project template is through the New Project Wizard (File -> New Project Wizard). After entering the project name and folder on the first panel, the second panel will ask you to specify an empty project or project template. Select project template. You will see a list of Design Templates projects that you have loaded prior as well as various "Baseline Pinout Designs" that contain the pinout and settings for a variety of development kits. If you don't see your design template in the list, click on the link that states install the Design Templates circled below:


Browse to the <project>.par file you downloaded, click next, followed by Finish, and your design template will be installed and displayed in the Project Navigator pane in Quartus.

Note: When a design is stored in the Design Store as a design template, it has been previously regression tested against the stated version of Quartus software. The regression ensures the design template passes analysis/synthesis/fitting/assembly steps in the Quartus design flow.

At the command-line, type the following command:

quartus_sh --platform_install –package <project directory>/an911_design_examples.par

Once the process completes, then type:

quartus_sh --platform –name an911_design_examples

Download   (The download link will expire on Oct. 22, 2021, 12:55 a.m., please refresh the page to get a new link.)
Quartus Prime VersionDownload Quartus Prime v20.3
Quartus Prime EditionPro
VendorIntel


Last updated on Dec. 3, 2020, 8:02 p.m.