Design Store

Stratix 10 PCIe Gen3 x8 DMA  

CategoryDesign Example
NameStratix 10 PCIe Gen3 x8 DMA
DescriptionThe design includes a high-performance DMA with an Avalon-MM interface that connects to the PCI Express Hard IP core. It transfers data either between on- chip memory and system memory or external memory and system memory. The reference design includes Linux software drivers that set up the DMA transfer. You can also use the software driver to measure and display the performance achieved for the transfers. This reference design allows you to evaluate the performance of the PCI Express protocol in using the Avalon-MM interface.
Operating SystemNone
IP Core
IP CoreHeading
Top level generated instrumentation fabricDebug & Performance
Altera SignalTap II AgentDebug and Performance
Stratix 10 External Memory InterfacesMemory Interfaces and Controllers
EMIF Architecture Component for the Stratix 10 Device FamilyInternal Components
EMIF Error Correction Code (ECC) ComponentInternal Components
EMIF Error Correction Code (ECC) Component for Stratix 10Internal Components
Avalon-MM Pipeline BridgeQsysInterconnect
Avalon-MM Clock Crossing BridgeQsysInterconnect
MM InterconnectQsysInterconnect
Avalon-ST Pipeline StageQsysInterconnect
Memory-Mapped DemultiplexerQsysInterconnect
Memory-Mapped MultiplexerQsysInterconnect
Avalon-MM Slave AgentQsysInterconnect
Avalon-ST Single Clock FIFOQsysInterconnect
Memory-Mapped Burst AdapterQsysInterconnect
Avalon-MM Slave TranslatorQsysInterconnect
Memory-Mapped Width AdapterQsysInterconnect
Avalon-MM Master AgentQsysInterconnect
Avalon-MM Master TranslatorQsysInterconnect
Memory-Mapped Traffic LimiterQsysInterconnect
Memory-Mapped RouterQsysInterconnect
On-Chip Memory (RAM or ROM)OnChipMemory
Reset ControllerQsysInterconnect
FamilyStratix 10
AN 829: PCI Express Avalon -MM DMA Reference DesignAN 829: PCI Express Avalon -MM DMA Reference Design
Development KitStratix 10 GX L-Tile Development Kit
Installation Package

Note: After downloading the design example, you must prepare the design template. The file you downloaded is of the form of a <project>.par file which contains a compressed version of your design files (similar to a .qar file) and metadata describing the project. The combination of this information is what constitutes a <project>.par file. In releases 16.0 or newer, you can simply double click on the <project>.par file and Quartus will launch that project.

The second means to bring up the project template is through the New Project Wizard (File -> New Project Wizard). After entering the project name and folder on the first panel, the second panel will ask you to specify an empty project or project template. Select project template. You will see a list of Design Templates projects that you have loaded prior as well as various "Baseline Pinout Designs" that contain the pinout and settings for a variety of development kits. If you don't see your design template in the list, click on the link that states install the Design Templates circled below:

Browse to the <project>.par file you downloaded, click next, followed by Finish, and your design template will be installed and displayed in the Project Navigator pane in Quartus.

Note: When a design is stored in the Design Store as a design template, it has been previously regression tested against the stated version of Quartus software. The regression ensures the design template passes analysis/synthesis/fitting/assembly steps in the Quartus design flow.

At the command-line, type the following command:

quartus_sh --platform_install –package <project directory>/Stratix10_PCIeGen3x8_DMA_18_0.par

Once the process completes, then type:

quartus_sh --platform –name Stratix10_PCIeGen3x8_DMA_18_0

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Last updated on April 14, 2020, 6:11 p.m.