Category | Design Example | ||||
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Name | Stratix 10 CvP Initialization Example Design | ||||
Description | This example design demonstrate Stratix 10 CvP using AVST PCIe HIP. | ||||
Operating System | None | ||||
IP Core |
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Version | 1.0 | ||||
Family | Stratix 10 | ||||
Device | 1SG280H | ||||
Documentation |
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Development Kit | Stratix 10 GX FPGA Development Kit | ||||
Installation Package | Note: After downloading the design example, you must prepare the design template. The file you downloaded is of the form of a <project>.par file which contains a compressed version of your design files (similar to a .qar file) and metadata describing the project. The combination of this information is what constitutes a <project>.par file. In releases 16.0 or newer, you can simply double click on the <project>.par file and Quartus will launch that project.
Browse to the <project>.par file you downloaded, click next, followed by Finish, and your design template will be installed and displayed in the Project Navigator pane in Quartus. Note: When a design is stored in the Design Store as a design template, it has been previously regression tested against the stated version of Quartus software. The regression ensures the design template passes analysis/synthesis/fitting/assembly steps in the Quartus design flow. At the command-line, type the following command:
Once the process completes, then type:
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Quartus Prime Version | Download Quartus Prime v17.1 | ||||
Quartus Prime Edition | Pro | ||||
Vendor | Intel |
Last updated on Oct. 10, 2018, 8:39 p.m.