Design Store


Intel Arria 10 FPGA Remote System Update via PCI Express*  


CategoryDesign Example
NameIntel Arria 10 FPGA Remote System Update via PCI Express*
DescriptionThis reference design demonstrates remote system update functionality on Arria® 10 FPGA Development Kit using PCI Express as the communication protocol. The configuration image from the host system is received via PCI Express in the Intel® Arria 10 device and then written into the serial flash by Modular Scatter-Gather DMA. The reconfiguration process of remote update is controlled by the dedicated remote system upgrade circuitry in the Intel Arria 10 device and manage via PCI Express.
Operating SystemNone
IP Core
IP CoreHeading
Reset ControllerQsysInterconnect
MM InterconnectQsysInterconnect
Memory-Mapped DemultiplexerQsysInterconnect
Memory-Mapped MultiplexerQsysInterconnect
Memory-Mapped Width AdapterQsysInterconnect
Avalon-ST Handshake Clock CrosserQsysInterconnect
Avalon-MM Slave TranslatorQsysInterconnect
Avalon-ST Pipeline StageQsysInterconnect
Avalon-MM Slave AgentQsysInterconnect
Avalon-ST Single Clock FIFOQsysInterconnect
Memory-Mapped RouterQsysInterconnect
Memory-Mapped Burst AdapterQsysInterconnect
Avalon-MM Master TranslatorQsysInterconnect
Memory-Mapped Traffic LimiterQsysInterconnect
Avalon-MM Master AgentQsysInterconnect
Arria 10 Hard IP for PCI ExpressPCIExpress
Arria 10 Transceiver Native PHYTransceiverPHY
Arria 10 FPLLClocksPLLsResets
Arria 10 Transceiver ATX PLLTransceiverPLL
IRQ MapperQsysInterconnect
Altera Remote UpdateConfigurationProgramming
Altera Remote Update CoreConfigurationProgramming
Avalon Remote Update ControllerConfiguration and Programming
Altera IOPLLClocksPLLsResets
Modular Scatter-Gather DMABridgesAndAdaptors
Read MasterQsysInterconnect
Write MasterQsysInterconnect
Modular SGDMA DispatcherBridgesAndAdaptors
Version1.0
FamilyArria 10
Device10AX115
Documentation
DocumentDescription
Intel Arria 10 FPGA Remote System Update via PCI Express*Intel Arria 10 FPGA Remote System Update via PCI Express* Design User Guide
Development KitArria 10 GX FPGA Development Kit
Installation Package

Note: After downloading the design example, you must prepare the design template. The file you downloaded is of the form of a <project>.par file which contains a compressed version of your design files (similar to a .qar file) and metadata describing the project. The combination of this information is what constitutes a <project>.par file. In releases 16.0 or newer, you can simply double click on the <project>.par file and Quartus will launch that project.

The second means to bring up the project template is through the New Project Wizard (File -> New Project Wizard). After entering the project name and folder on the first panel, the second panel will ask you to specify an empty project or project template. Select project template. You will see a list of Design Templates projects that you have loaded prior as well as various "Baseline Pinout Designs" that contain the pinout and settings for a variety of development kits. If you don't see your design template in the list, click on the link that states install the Design Templates circled below:


Browse to the <project>.par file you downloaded, click next, followed by Finish, and your design template will be installed and displayed in the Project Navigator pane in Quartus.

Note: When a design is stored in the Design Store as a design template, it has been previously regression tested against the stated version of Quartus software. The regression ensures the design template passes analysis/synthesis/fitting/assembly steps in the Quartus design flow.

At the command-line, type the following command:

quartus_sh --platform_install –package <project directory>/arria10_pcie_rsu.par

Once the process completes, then type:

quartus_sh --platform –name arria10_pcie_rsu

Download   (The download link will expire on April 17, 2021, 8:29 a.m., please refresh the page to get a new link.)
Quartus Prime VersionDownload Quartus Prime v20.4
Quartus Prime EditionPro
VendorIntel


Last updated on April 12, 2021, 8:09 p.m.