Design Store


12G-SDI Audio Reference Design  


CategoryDesign Example
Name12G-SDI Audio Reference Design
DescriptionThe 12G-SDI Audio Embed/Extract Reference Design provides an application example for embedding and de-embedding of digital audio data into a 12G-SDI video signal.
Operating SystemNone
IP Core
IP CoreHeading
ALTCLKCTRLClocksPLLsResets
Altera IOPLLClocksPLLsResets
Arria 10 FPLLClocksPLLsResets
Reset ControllerQsysInterconnect
Avalon-MM Clock Crossing BridgeQsysInterconnect
Avalon-ST Dual Clock FIFOQsysInterconnect
MM InterconnectQsysInterconnect
Avalon-MM Master TranslatorQsysInterconnect
Avalon-MM Slave TranslatorQsysInterconnect
Avalon-MM Master AgentQsysInterconnect
Avalon-MM Slave AgentQsysInterconnect
Avalon-ST Single Clock FIFOQsysInterconnect
Memory-Mapped RouterQsysInterconnect
Memory-Mapped Traffic LimiterQsysInterconnect
Memory-Mapped DemultiplexerQsysInterconnect
Memory-Mapped MultiplexerQsysInterconnect
Avalon-MM Pipeline BridgeQsysInterconnect
altera_jtag_avalon_masterQsysInterconnect
Avalon-ST JTAG InterfaceQsysInterconnect
Avalon-ST Packets to Bytes ConverterQsysInterconnect
Avalon-ST Channel AdapterQsysInterconnect
Avalon Packets to Transaction ConverterQsysInterconnect
Avalon-ST Timing AdapterQsysInterconnect
Avalon-ST Bytes to Packets ConverterQsysInterconnect
Arria 10 Transceiver Native PHYTransceiverPHY
Transceiver PHY Reset ControllerTransceiverPHY
SDI IITransceiverPHY
FIFOOnChipMemory
Audio EmbedAudio & Video
Audio ExtractAudio & Video
Top level generated instrumentation fabricDebug & Performance
Altera Arria 10 XCVR Reset SequencerOther
Version1.0
FamilyArria 10
Device10AS066
Documentation
DocumentDescription
12G-SDI Audio Reference Design User Guide12G-SDI Audio Reference Design User Guide
Development KitArria 10 SoC Development Kit
Installation Package

Note: After downloading the design example, you must prepare the design template. The file you downloaded is of the form of a <project>.par file which contains a compressed version of your design files (similar to a .qar file) and metadata describing the project. The combination of this information is what constitutes a <project>.par file. In releases 16.0 or newer, you can simply double click on the <project>.par file and Quartus will launch that project.

The second means to bring up the project template is through the New Project Wizard (File -> New Project Wizard). After entering the project name and folder on the first panel, the second panel will ask you to specify an empty project or project template. Select project template. You will see a list of Design Templates projects that you have loaded prior as well as various "Baseline Pinout Designs" that contain the pinout and settings for a variety of development kits. If you don't see your design template in the list, click on the link that states install the Design Templates circled below:


Browse to the <project>.par file you downloaded, click next, followed by Finish, and your design template will be installed and displayed in the Project Navigator pane in Quartus.

Note: When a design is stored in the Design Store as a design template, it has been previously regression tested against the stated version of Quartus software. The regression ensures the design template passes analysis/synthesis/fitting/assembly steps in the Quartus design flow.

At the command-line, type the following command:

quartus_sh --platform_install –package <project directory>/top.par

Once the process completes, then type:

quartus_sh --platform –name top

Download   (The download link will expire on June 23, 2021, 9:28 a.m., please refresh the page to get a new link.)
Quartus Prime VersionDownload Quartus Prime v20.1
Quartus Prime EditionPro
VendorIntel


Last updated on May 4, 2021, 5:10 a.m.