|Name||Agilex I/O PLL Reconfiguration|
|Description||This design example uses a AGFB014R24A2E3VR0 device to demonstrate the implementation of the following three different I/O PLL reconfiguration option using the IOPLL Reconfig IP core.|
• .mif streaming
• Advanced mode
• Clock gating
This design example consists of the IOPLL IP core, IOPLL Reconfig IP core, In-
System Sources & Probes Intel FPGA IP core and Reset Release Intel FPGA IP.
|Development Kit||Agilex F-Series Transceiver-SoC Development Kit|
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Note: After downloading the design example, you must prepare the design template. The file you downloaded is of the form of a <project>.par file which contains a compressed version of your design files (similar to a .qar file) and metadata describing the project. The combination of this information is what constitutes a <project>.par file. In releases 16.0 or newer, you can simply double click on the <project>.par file and Quartus will launch that project.
Browse to the <project>.par file you downloaded, click next, followed by Finish, and your design template will be installed and displayed in the Project Navigator pane in Quartus.
Note: When a design is stored in the Design Store as a design template, it has been previously regression tested against the stated version of Quartus software. The regression ensures the design template passes analysis/synthesis/fitting/assembly steps in the Quartus design flow.
At the command-line, type the following command:
Once the process completes, then type:
|Quartus Prime Version||Download Quartus Prime v19.4|
|Quartus Prime Edition||Pro|
Last updated on April 28, 2020, 6:20 p.m.