Design Store


Intel® Stratix® 10 H-tile CvP Example Design for Initialization mode  


CategoryDesign Example
NameIntel® Stratix® 10 H-tile CvP Example Design for Initialization mode
DescriptionThis design demonstrate the CvP Initialization mode on the Intel® Straitx® 10 GX H-tile development kit.
Operating SystemNone
IP Core
IP CoreHeading
Reset ControllerQsysInterconnect
Altera IOPLLClocksPLLsResets
MM InterconnectQsysInterconnect
Memory-Mapped MultiplexerQsysInterconnect
Memory-Mapped RouterQsysInterconnect
Avalon-MM Slave AgentQsysInterconnect
Avalon-MM Master TranslatorQsysInterconnect
Memory-Mapped DemultiplexerQsysInterconnect
Memory-Mapped Burst AdapterQsysInterconnect
Avalon-ST Single Clock FIFOQsysInterconnect
Avalon-MM Slave TranslatorQsysInterconnect
Avalon-MM Master AgentQsysInterconnect
On-Chip Memory (RAM or ROM)OnChipMemory
Top level generated instrumentation fabricDebug & Performance
Version1.0
FamilyStratix 10
Device1SG280H
Documentation
DocumentDescription
Intel® Stratix® 10 Configuration via Protocol (CvP) Implementation User GuideConfiguration via Protocol (CvP) is a configuration scheme supported in Intel® Stratix® 10 family. The CvP configuration scheme creates separate images for the periphery and core logic. You can store the periphery image in a local configuration device and the core image in host memory, reducing system costs and increasing the security for the proprietary core image. CvP configures the Intel® FPGA fabric through the PCI Express* ( PCIe* ) link, and is available for Endpoint variants only. This document describes the CvP configuration scheme for Intel® Stratix® 10 device family. The CvP configuration scheme targets core fabric configuration through PCIe* link, which means it only supports FPGA Configuration First Mode even you use Intel® Stratix® 10 SoC devices.
Development KitStratix 10 GX FPGA Development Kit
Installation Package

Note: After downloading the design example, you must prepare the design template. The file you downloaded is of the form of a <project>.par file which contains a compressed version of your design files (similar to a .qar file) and metadata describing the project. The combination of this information is what constitutes a <project>.par file. In releases 16.0 or newer, you can simply double click on the <project>.par file and Quartus will launch that project.

The second means to bring up the project template is through the New Project Wizard (File -> New Project Wizard). After entering the project name and folder on the first panel, the second panel will ask you to specify an empty project or project template. Select project template. You will see a list of Design Templates projects that you have loaded prior as well as various "Baseline Pinout Designs" that contain the pinout and settings for a variety of development kits. If you don't see your design template in the list, click on the link that states install the Design Templates circled below:


Browse to the <project>.par file you downloaded, click next, followed by Finish, and your design template will be installed and displayed in the Project Navigator pane in Quartus.

Note: When a design is stored in the Design Store as a design template, it has been previously regression tested against the stated version of Quartus software. The regression ensures the design template passes analysis/synthesis/fitting/assembly steps in the Quartus design flow.

At the command-line, type the following command:

quartus_sh --platform_install –package <project directory>/top.par

Once the process completes, then type:

quartus_sh --platform –name top

Download   (The download link will expire on May 26, 2020, 9:32 p.m., please refresh the page to get a new link.)
Total Downloads3 (From 06 Nov 2019 to 06 Dec 2019)
Quartus Prime VersionDownload Quartus Prime v19.3
Quartus Prime EditionPro
VendorIntel


Last updated on Nov. 6, 2019, 4:58 p.m.