|Name||Intel® Stratix® 10 H-tile CvP Example Design for Initialization mode|
|Description||This design demonstrate the CvP Initialization mode on the Intel® Straitx® 10 GX H-tile development kit.|
|Development Kit||Stratix 10 GX FPGA Development Kit|
Download (The download link will expire on May 26, 2020, 9:32 p.m., please refresh the page to get a new link.)
Note: After downloading the design example, you must prepare the design template. The file you downloaded is of the form of a <project>.par file which contains a compressed version of your design files (similar to a .qar file) and metadata describing the project. The combination of this information is what constitutes a <project>.par file. In releases 16.0 or newer, you can simply double click on the <project>.par file and Quartus will launch that project.
Browse to the <project>.par file you downloaded, click next, followed by Finish, and your design template will be installed and displayed in the Project Navigator pane in Quartus.
Note: When a design is stored in the Design Store as a design template, it has been previously regression tested against the stated version of Quartus software. The regression ensures the design template passes analysis/synthesis/fitting/assembly steps in the Quartus design flow.
At the command-line, type the following command:
Once the process completes, then type:
|Total Downloads||3 (From 06 Nov 2019 to 06 Dec 2019)|
|Quartus Prime Version||Download Quartus Prime v19.3|
|Quartus Prime Edition||Pro|
Last updated on Nov. 6, 2019, 4:58 p.m.