Design Store


Agilex Mailbox Client Intel FPGA IP Core Design Example(QSPI flash Access and Remote System Update)  


CategoryDesign Example
NameAgilex Mailbox Client Intel FPGA IP Core Design Example(QSPI flash Access and Remote System Update)
DescriptionThis reference design implements the Mailbox Client Intel FPGA IP Core in Agilex FPGA.

The Mailbox Client Intel FPGA IP is a bridge between a host and the Secure Device Manager(SDM). You use the Mailbox Client Intel FPGA IP to send commands and receive status from SDM peripheral clients. The Mailbox Client Intel FPGA IP is an Avalon MM slave component that must connect
to an Avalon MM master.

In this reference design, JTAG-to-Avalon Master act as the host controller connecting to Mailbox Client Intel FPGA IP core. The JTAG-to-Avalon Master Bridge IP translate the commands it receives from the System Console to Avalon Memory-Mapped (Avalon MM) format that the Mailbox Client Intel FPGA IP requires. Mailbox Client Intel FPGA IP: drives commands and receives responses from the SDM.

The rsu1.tcl script provides examples to perform the available command functions supported by SDM. You can run the functions available in the rsu1.tcl script via System Console of the Intel Quartus Prime software to perform the following operations,
- Read FPGA IDCODE
- Read FPGA CHIP ID
- QPSI flash access operations such as program QSPI flash with .rpd file.
- Remote System Update(RSU) operations such as reading RSU status and trigger reconfiguration from the data source which can be either an application image or factory image.

The rsu1.tcl script can be downloaded from the link provided below.
https://www.intel.com/content/dam/altera-www/global/en_US/others/support/devices/configuration/rsu1.tcl

For more details,
1. Refer to Mailbox Client Intel FPGA IP User Guide
https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/ug-20087.pdf

2. Refer to Chapter 4. Remote System Update(RSU) in Intel Agilex Configuration User Guide
https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/hb/agilex/ug-ag-config.pdf
Operating SystemOther
IP Core
IP CoreHeading
Altera In-System Sources & ProbesSimulationDebugVerification
Reset ControllerQsysInterconnect
MM InterconnectQsysInterconnect
Avalon-MM Master TranslatorQsysInterconnect
Avalon-MM Slave TranslatorQsysInterconnect
altera_config_stream_endpointDebug & Performance
altera_jtag_avalon_masterQsysInterconnect
Avalon Packets to Transaction ConverterQsysInterconnect
Avalon-ST Single Clock FIFOQsysInterconnect
Avalon-ST Channel AdapterQsysInterconnect
Avalon-ST Bytes to Packets ConverterQsysInterconnect
Avalon-ST JTAG InterfaceQsysInterconnect
Avalon-ST Packets to Bytes ConverterQsysInterconnect
Avalon-ST Timing AdapterQsysInterconnect
Top level generated instrumentation fabricDebug & Performance
Altera SDM Mbox BridgeConfiguration and Programming
Altera SDM GPO Configuration and Programming
Altera SDM GPI Configuration and Programming
Altera FPGA2SDM BridgeConfiguration and Programming
Altera SDM IRQ Configuration and Programming
Altera SDM2FPGA BridgeConfiguration and Programming
Avalon-ST Handshake Clock CrosserQsysInterconnect
Memory-Mapped MultiplexerQsysInterconnect
Version19.3
FamilyAgilex
DeviceAGFA014_R0
Documentation
DocumentDescription
Agilex Mailbox Client Intel FPGA IP Core Design Example(QSPI flash Access and Remote System Update)-
Development KitAgilex F-Series Transceiver-SoC Development Kit
Installation Package

Note: After downloading the design example, you must prepare the design template. The file you downloaded is of the form of a <project>.par file which contains a compressed version of your design files (similar to a .qar file) and metadata describing the project. The combination of this information is what constitutes a <project>.par file. In releases 16.0 or newer, you can simply double click on the <project>.par file and Quartus will launch that project.

The second means to bring up the project template is through the New Project Wizard (File -> New Project Wizard). After entering the project name and folder on the first panel, the second panel will ask you to specify an empty project or project template. Select project template. You will see a list of Design Templates projects that you have loaded prior as well as various "Baseline Pinout Designs" that contain the pinout and settings for a variety of development kits. If you don't see your design template in the list, click on the link that states install the Design Templates circled below:


Browse to the <project>.par file you downloaded, click next, followed by Finish, and your design template will be installed and displayed in the Project Navigator pane in Quartus.

Note: When a design is stored in the Design Store as a design template, it has been previously regression tested against the stated version of Quartus software. The regression ensures the design template passes analysis/synthesis/fitting/assembly steps in the Quartus design flow.

At the command-line, type the following command:

quartus_sh --platform_install –package <project directory>/top.par

Once the process completes, then type:

quartus_sh --platform –name top

Download   (The download link will expire on Oct. 22, 2021, 1:31 a.m., please refresh the page to get a new link.)
Quartus Prime VersionDownload Quartus Prime v19.3
Quartus Prime EditionPro
VendorIntel


Last updated on Sept. 29, 2020, 10:56 p.m.