Intel® Arria® 10 FPGA – Multi-Rate SDI II Pass-Through Using Video and Image Processing Pipeline Reference Design

Intel® Arria® 10 FPGA – Multi-Rate SDI II Pass-Through Using Video and Image Processing Pipeline Reference Design

714772
8/2/2019

Introduction

The Intel® Arria® 10 FPGA SDI II reference design demonstrates the multi-rate (up to 12G-SDI) pass-through video data with an external voltage-controlled crystal oscillator (VCXO). The design uses key Video and Image Processing Suite (VIP) Intel FPGA IP cores, such as Clocked Video Input II (CVI II) Intel FPGA IP, Clocked Video Output II (CVO II) Intel FPGA IP, Frame Buffer II (VFB II) Intel FPGA IP, and Switch II Intel FPGA IP for pass-through implementation.

Design Details

Device Family

Intel® Arria® 10 FPGAs and SoC FPGAs

Quartus Edition

Intel® Quartus® Prime Pro Edition

Quartus Version

19.2

IP Cores (47)
IP Core IP Core Category
Top level generated instrumentation fabric Debug & Performance
Altera Arria 10 XCVR Reset Sequencer Other
Nios II Gen2 Processor NiosII
Nios II Gen2 Processor Unit NiosII
On-Chip Memory (RAM or ROM) OnChipMemory
Arria 10 External Memory Interfaces ExternalMemoryInterfaces
EMIF Core Component for 20nm Families ExternalMemoryInterfaces
EMIF Error Correction Code (ECC) Component Internal Components
EMIF Error Correction Code (ECC) Component for Arria 10 Internal Components
Arria 10 External Memory Interfaces Debug Component ExternalMemoryInterfaces
alt_mem_if JTAG to Avalon Master Bridge BridgesAndAdaptors
Avalon-ST JTAG Interface QsysInterconnect
Avalon-ST Packets to Bytes Converter QsysInterconnect
Avalon-ST Channel Adapter QsysInterconnect
Avalon Packets to Transaction Converter QsysInterconnect
Avalon-ST Timing Adapter QsysInterconnect
Avalon-ST Single Clock FIFO QsysInterconnect
Reset Controller QsysInterconnect
Avalon-ST Bytes to Packets Converter QsysInterconnect
MM Interconnect QsysInterconnect
Avalon-MM Master Translator QsysInterconnect
Avalon-MM Slave Translator QsysInterconnect
Avalon-MM Pipeline Bridge QsysInterconnect
JTAG UART ConfigurationProgramming
System ID Peripheral Other
Clocked Video Input II (4K Ready) AudioVideo
Video and Image Processing Suite Other
Clocked Video Output II (4K Ready) AudioVideo
Video Input Bridge AudioVideo
alt_vip_cvo_core AudioVideo
Switch II (4K Ready) Video and Image Processing
Frame Buffer II (4K Ready) AudioVideo
Interval Timer Peripherals
Memory-Mapped Demultiplexer QsysInterconnect
Memory-Mapped Multiplexer QsysInterconnect
Avalon-ST Handshake Clock Crosser QsysInterconnect
Avalon-MM Master Agent QsysInterconnect
Avalon-MM Slave Agent QsysInterconnect
Memory-Mapped Router QsysInterconnect
IRQ Mapper QsysInterconnect
IRQ Clock Crosser QsysInterconnect
ALTCLKCTRL ClocksPLLsResets
Arria 10 Transceiver Native PHY TransceiverPHY
Transceiver PHY Reset Controller TransceiverPHY
SDI II TransceiverPHY
Arria 10 FPLL ClocksPLLsResets
Altera IOPLL ClocksPLLsResets

Detailed Description

Prepare the design template in the Quartus Prime software GUI (version 14.1 and later)


Note: After downloading the design example, you must prepare the design template. The file you downloaded is of the form of a <project>.par file which contains a compressed version of your design files (similar to a .qar file) and metadata describing the project. The combination of this information is what constitutes a <project>.par file. In releases 16.0 or newer, you can simply double click on the <project>.par file and Quartus will launch that project.


The second means to bring up the project template is through the New Project Wizard (File -> New Project Wizard). After entering the project name and folder on the first panel, the second panel will ask you to specify an empty project or project template. Select project template. You will see a list of Design Templates projects that you have loaded prior as well as various "Baseline Pinout Designs" that contain the pinout and settings for a variety of development kits. If you don't see your design template in the list, click on the link that states install the Design Templates circled below:



Browse to the <project>.par file you downloaded, click next, followed by Finish, and your design template will be installed and displayed in the Project Navigator pane in Quartus.


Note: When a design is stored in the Design Store as a design template, it has been previously regression tested against the stated version of Quartus software. The regression ensures the design template passes analysis/synthesis/fitting/assembly steps in the Quartus design flow.



Prepare the design template in the Quartus Prime software command-line


At the command-line, type the following command:

quartus_sh --platform_install -package <project directory>/<project>.par


Once the process completes, then type:

quartus_sh --platform -name <project>



Note:

* ACDS Version: 19.2.0 Pro


Design Details

Device Family

Intel® Arria® 10 FPGAs and SoC FPGAs

Quartus Edition

Intel® Quartus® Prime Pro Edition

Quartus Version

19.2