Design Store

Intel® Arria® 10 GX Device Multi-Rate SDI II Pass-Through Using Video & Image Processing Pipeline Reference Design   

CategoryDesign Example
NameIntel® Arria® 10 GX Device Multi-Rate SDI II Pass-Through Using Video & Image Processing Pipeline Reference Design
DescriptionThe Intel Arria 10 SDI II reference design demonstrates the multi-rate (up to 12G-SDI) pass-through video data with external voltage-controlled crystal oscillator (VCXO). The design uses key Video and Image Processing Suite (VIP) IP Cores, such as Clocked Video Input II (4k ready) Intel FPGA IP (CVI II), Clocked Video Output II (4k ready) Intel FPGA IP (CVO II), Frame Buffer II (4k ready) Intel FPGA IP (VFB II) and Switch II (4k ready) Intel FPGA IP for pass-through implementation.
Operating SystemNone
IP Core
IP CoreHeading
Top level generated instrumentation fabricDebug & Performance
Altera Arria 10 XCVR Reset SequencerOther
Nios II Gen2 ProcessorNiosII
Nios II Gen2 Processor UnitNiosII
On-Chip Memory (RAM or ROM)OnChipMemory
Arria 10 External Memory InterfacesExternalMemoryInterfaces
EMIF Core Component for 20nm FamiliesExternalMemoryInterfaces
EMIF Error Correction Code (ECC) ComponentInternal Components
EMIF Error Correction Code (ECC) Component for Arria 10Internal Components
Arria 10 External Memory Interfaces Debug ComponentExternalMemoryInterfaces
alt_mem_if JTAG to Avalon Master BridgeBridgesAndAdaptors
Avalon-ST JTAG InterfaceQsysInterconnect
Avalon-ST Packets to Bytes ConverterQsysInterconnect
Avalon-ST Channel AdapterQsysInterconnect
Avalon Packets to Transaction ConverterQsysInterconnect
Avalon-ST Timing AdapterQsysInterconnect
Avalon-ST Single Clock FIFOQsysInterconnect
Reset ControllerQsysInterconnect
Avalon-ST Bytes to Packets ConverterQsysInterconnect
MM InterconnectQsysInterconnect
Avalon-MM Master TranslatorQsysInterconnect
Avalon-MM Slave TranslatorQsysInterconnect
Avalon-MM Pipeline BridgeQsysInterconnect
JTAG UARTConfigurationProgramming
System ID PeripheralOther
Clocked Video Input II (4K Ready)AudioVideo
Video and Image Processing SuiteOther
Clocked Video Output II (4K Ready)AudioVideo
Video Input BridgeAudioVideo
Switch II (4K Ready)Video and Image Processing
Frame Buffer II (4K Ready)AudioVideo
Interval TimerPeripherals
Memory-Mapped DemultiplexerQsysInterconnect
Memory-Mapped MultiplexerQsysInterconnect
Avalon-ST Handshake Clock CrosserQsysInterconnect
Avalon-MM Master AgentQsysInterconnect
Avalon-MM Slave AgentQsysInterconnect
Memory-Mapped RouterQsysInterconnect
IRQ MapperQsysInterconnect
IRQ Clock CrosserQsysInterconnect
Arria 10 Transceiver Native PHYTransceiverPHY
Transceiver PHY Reset ControllerTransceiverPHY
SDI IITransceiverPHY
Arria 10 FPLLClocksPLLsResets
Altera IOPLLClocksPLLsResets
FamilyArria 10
Intel® Arria® 10 GX Device Multi-Rate SDI II PassThrough Using Video & Image Processing Pipeline Reference Design Tutorial-
Development KitArria 10 GX FPGA Development Kit
Installation Package

Note: After downloading the design example, you must prepare the design template. The file you downloaded is of the form of a <project>.par file which contains a compressed version of your design files (similar to a .qar file) and metadata describing the project. The combination of this information is what constitutes a <project>.par file. In releases 16.0 or newer, you can simply double click on the <project>.par file and Quartus will launch that project.

The second means to bring up the project template is through the New Project Wizard (File -> New Project Wizard). After entering the project name and folder on the first panel, the second panel will ask you to specify an empty project or project template. Select project template. You will see a list of Design Templates projects that you have loaded prior as well as various "Baseline Pinout Designs" that contain the pinout and settings for a variety of development kits. If you don't see your design template in the list, click on the link that states install the Design Templates circled below:

Browse to the <project>.par file you downloaded, click next, followed by Finish, and your design template will be installed and displayed in the Project Navigator pane in Quartus.

Note: When a design is stored in the Design Store as a design template, it has been previously regression tested against the stated version of Quartus software. The regression ensures the design template passes analysis/synthesis/fitting/assembly steps in the Quartus design flow.

At the command-line, type the following command:

quartus_sh --platform_install –package <project directory>/a10_mr_sdi2_vip.par

Once the process completes, then type:

quartus_sh --platform –name a10_mr_sdi2_vip

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Last updated on Aug. 20, 2020, 6:05 p.m.