Design Store

AN881: PCIe Gen3x16 Avalon-MM DMA with DDR4 and HBM2 Reference Design  

CategoryDesign Example
NameAN881: PCIe Gen3x16 Avalon-MM DMA with DDR4 and HBM2 Reference Design
DescriptionThis reference design demonstrates the performance of the Avalon-MM Intel® Stratix® 10 Hard IP+ for PCI Express, a high-performance DMA controller with two types of memory solutions: external (DDR4) and HBM2 memories. The Read Data Mover moves data from the system memory to the external or HBM2 memory in Avalon-MM space . The Write Data Mover moves data from the external or HBM2 memory in the application logic to the system memory in PCIe* space.
Operating SystemNone
IP Core
IP CoreHeading
Top level generated instrumentation fabricDebug & Performance
Avalon-ST Single Clock FIFOQsysInterconnect
MM InterconnectQsysInterconnect
Memory-Mapped RouterQsysInterconnect
Memory-Mapped Traffic LimiterQsysInterconnect
Memory-Mapped DemultiplexerQsysInterconnect
Avalon-MM Slave TranslatorQsysInterconnect
Avalon-MM Slave AgentQsysInterconnect
Memory-Mapped Burst AdapterQsysInterconnect
Memory-Mapped MultiplexerQsysInterconnect
Avalon-MM Master AgentQsysInterconnect
Avalon-MM Master TranslatorQsysInterconnect
Reset ControllerQsysInterconnect
Avalon-MM Clock Crossing BridgeQsysInterconnect
Altera IOPLLClocksPLLsResets
AXI TranslatorHardProcessorComponents
AXI Slave AgentHardProcessorComponents
Stratix 10 External Memory InterfacesMemory Interfaces and Controllers
EMIF Architecture Component for the Stratix 10 Device FamilyInternal Components
Arria 10 External Memory Interfaces Debug ComponentExternalMemoryInterfaces
Avalon-MM Pipeline BridgeQsysInterconnect
alt_mem_if JTAG to Avalon Master BridgeBridgesAndAdaptors
Avalon Packets to Transaction ConverterQsysInterconnect
Avalon-ST Channel AdapterQsysInterconnect
Avalon-ST Bytes to Packets ConverterQsysInterconnect
Avalon-ST JTAG InterfaceQsysInterconnect
Avalon-ST Packets to Bytes ConverterQsysInterconnect
Avalon-ST Timing AdapterQsysInterconnect
AXI BridgeMemory Mapped
FamilyStratix 10
AN 881: PCI Express* Gen3 x16 Avalon®-MM DMA with DDR4 and HBM2 Memory Reference Design-
Development KitStratix 10 MX FPGA Development Kit
Installation Package

Note: After downloading the design example, you must prepare the design template. The file you downloaded is of the form of a <project>.par file which contains a compressed version of your design files (similar to a .qar file) and metadata describing the project. The combination of this information is what constitutes a <project>.par file. In releases 16.0 or newer, you can simply double click on the <project>.par file and Quartus will launch that project.

The second means to bring up the project template is through the New Project Wizard (File -> New Project Wizard). After entering the project name and folder on the first panel, the second panel will ask you to specify an empty project or project template. Select project template. You will see a list of Design Templates projects that you have loaded prior as well as various "Baseline Pinout Designs" that contain the pinout and settings for a variety of development kits. If you don't see your design template in the list, click on the link that states install the Design Templates circled below:

Browse to the <project>.par file you downloaded, click next, followed by Finish, and your design template will be installed and displayed in the Project Navigator pane in Quartus.

Note: When a design is stored in the Design Store as a design template, it has been previously regression tested against the stated version of Quartus software. The regression ensures the design template passes analysis/synthesis/fitting/assembly steps in the Quartus design flow.

At the command-line, type the following command:

quartus_sh --platform_install –package <project directory>/pcie_to_hbm2_ddr4_top.par

Once the process completes, then type:

quartus_sh --platform –name pcie_to_hbm2_ddr4_top

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Last updated on Feb. 17, 2021, 11:04 p.m.