Intel® MAX® 10 FPGA – Software Design Example for Avalon® Streaming (Avalon-ST) Interface Configuration Design Example

Intel® MAX® 10 FPGA – Software Design Example for Avalon® Streaming (Avalon-ST) Interface Configuration Design Example

715032
2/10/2020

Introduction

In this design, we demonstrate how to configure the Intel® Stratix® 10 FPGA using embedded software for microprocessors. To illustrate the example, we use the Nios® II processor as the host to perform the Intel Stratix 10 FPGA configuration. This design is based on the Intel Stratix 10 SoC FPGA Development Kit. The Nios II processor that we use is programmed onto the Intel MAX® 10 device on the board, which serves as the system controller for the development kit. The Nios II processor reads the Intel Stratix 10 FPGA configuration image from the flash and sends it to the Intel Stratix 10 FPGA via the Avalon® streaming (Avalon-ST) x16 interface. This software example is written for the Nios II processor; however, it should be portable to other microprocessor architectures by modifying the source codes.

Development Kit

Intel® Stratix® 10 SX SoC Development Kits

Design Details

Device Family

Intel® MAX® 10 FPGAs
Quartus Edition

Intel® Quartus® Prime Standard Edition
Quartus Version

19.1
IP Cores (0)

Detailed Description

Prepare the design template in the Quartus Prime software GUI (version 14.1 and later)


Note: After downloading the design example, you must prepare the design template. The file you downloaded is of the form of a <project>.par file which contains a compressed version of your design files (similar to a .qar file) and metadata describing the project. The combination of this information is what constitutes a <project>.par file. In releases 16.0 or newer, you can simply double click on the <project>.par file and Quartus will launch that project.


The second means to bring up the project template is through the New Project Wizard (File -> New Project Wizard). After entering the project name and folder on the first panel, the second panel will ask you to specify an empty project or project template. Select project template. You will see a list of Design Templates projects that you have loaded prior as well as various "Baseline Pinout Designs" that contain the pinout and settings for a variety of development kits. If you don't see your design template in the list, click on the link that states install the Design Templates circled below:



Browse to the <project>.par file you downloaded, click next, followed by Finish, and your design template will be installed and displayed in the Project Navigator pane in Quartus.


Note: When a design is stored in the Design Store as a design template, it has been previously regression tested against the stated version of Quartus software. The regression ensures the design template passes analysis/synthesis/fitting/assembly steps in the Quartus design flow.



Prepare the design template in the Quartus Prime software command-line


At the command-line, type the following command:

quartus_sh --platform_install -package <project directory>/<project>.par


Once the process completes, then type:

quartus_sh --platform -name <project>



Note:

* ACDS Version: 19.1.0 Standard


Development Kit

Intel® Stratix® 10 SX SoC Development Kits

Design Details

Device Family

Intel® MAX® 10 FPGAs
Quartus Edition

Intel® Quartus® Prime Standard Edition
Quartus Version

19.1