|Name||Software Design Example for Configuration via Avalon-ST (AVST)|
|Description||In this design, we demonstrate how to configure the Stratix 10 FPGA using embedded software for microprocessor. To illustrate the example, we use the Nios II processor as the host to perform the Stratix 10 configuration. This design is based on the Intel Stratix 10 SoC FPGA development kit. The Nios II processor that we use is programmed onto the MAX10 device on the board, in which it serves as system controller for the development kit. Nios II reads the Stratix 10 configuration image from the flash and send to the Stratix 10 via the AVST x16 interface. This software example is written for Nios II processor; however, it should be portable to other microprocessor architecture by modifying the source codes.|
|Development Kit||Stratix 10 SX SoC Development Kit (MAX10 System Contoller)|
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Note: After downloading the design example, you must prepare the design template. The file you downloaded is of the form of a <project>.par file which contains a compressed version of your design files (similar to a .qar file) and metadata describing the project. The combination of this information is what constitutes a <project>.par file. In releases 16.0 or newer, you can simply double click on the <project>.par file and Quartus will launch that project.
Browse to the <project>.par file you downloaded, click next, followed by Finish, and your design template will be installed and displayed in the Project Navigator pane in Quartus.
Note: When a design is stored in the Design Store as a design template, it has been previously regression tested against the stated version of Quartus software. The regression ensures the design template passes analysis/synthesis/fitting/assembly steps in the Quartus design flow.
At the command-line, type the following command:
Once the process completes, then type:
|Quartus Prime Version||Download Quartus Prime v19.1|
|Quartus Prime Edition||Standard|
Last updated on Aug. 17, 2020, 5:22 p.m.