Design Store

AN 888: PHY Lite for Parallel Interface Reference Design with Dynamic Reconfiguration for Intel® Stratix® 10 Devices  

CategoryDesign Example
NameAN 888: PHY Lite for Parallel Interface Reference Design with Dynamic Reconfiguration for Intel® Stratix® 10 Devices
DescriptionThe PHY Lite reference design demonstrates the usage of dynamic reconfiguration feature using the PHY Lite for Parallel Interfaces Intel® Stratix® 10 FPGA IP cores. Two instances of PHY Lite for Parallel Interfaces Intel Stratix 10 FPGA IP cores are placed in different I/O tiles on a single FPGA. These PHY Lite instances are loopback
using the HiLo loopback card. One PHY Lite instance is configured as a transmitter and the other PHY Lite instance is configured as a receiver.
Operating SystemNone
IP Core
IP CoreHeading
Top level generated instrumentation fabricDebug & Performance
Altera SignalTap II AgentDebug and Performance
Altera PHYLite for Parallel InterfacesTransceiver PHY
PHYLite Core Component for 14nm Familiesaltera_emif
PIO (Parallel I/O)Other
Nios II Gen2 ProcessorNiosII
Nios II Gen2 Processor UnitNiosII
Avalon-MM Pipeline BridgeQsysInterconnect
MM InterconnectQsysInterconnect
Avalon-ST Single Clock FIFOQsysInterconnect
Memory-Mapped MultiplexerQsysInterconnect
Avalon-MM Slave AgentQsysInterconnect
Memory-Mapped DemultiplexerQsysInterconnect
Avalon-MM Master TranslatorQsysInterconnect
Memory-Mapped RouterQsysInterconnect
Avalon-MM Slave TranslatorQsysInterconnect
Avalon-MM Master AgentQsysInterconnect
IRQ MapperQsysInterconnect
On-Chip Memory (RAM or ROM)OnChipMemory
Reset ControllerQsysInterconnect
JTAG UARTConfigurationProgramming
FamilyStratix 10
PHY Lite for Parallel Interfaces Reference Design with Dynamic Reconfiguration for Intel® Stratix® 10 Devices-
Development KitStratix 10 GX FPGA Development Kit
Installation Package

Note: After downloading the design example, you must prepare the design template. The file you downloaded is of the form of a <project>.par file which contains a compressed version of your design files (similar to a .qar file) and metadata describing the project. The combination of this information is what constitutes a <project>.par file. In releases 16.0 or newer, you can simply double click on the <project>.par file and Quartus will launch that project.

The second means to bring up the project template is through the New Project Wizard (File -> New Project Wizard). After entering the project name and folder on the first panel, the second panel will ask you to specify an empty project or project template. Select project template. You will see a list of Design Templates projects that you have loaded prior as well as various "Baseline Pinout Designs" that contain the pinout and settings for a variety of development kits. If you don't see your design template in the list, click on the link that states install the Design Templates circled below:

Browse to the <project>.par file you downloaded, click next, followed by Finish, and your design template will be installed and displayed in the Project Navigator pane in Quartus.

Note: When a design is stored in the Design Store as a design template, it has been previously regression tested against the stated version of Quartus software. The regression ensures the design template passes analysis/synthesis/fitting/assembly steps in the Quartus design flow.

At the command-line, type the following command:

quartus_sh --platform_install –package <project directory>/phylite_top.par

Once the process completes, then type:

quartus_sh --platform –name phylite_top

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Last updated on June 13, 2019, 4:16 a.m.