|Name||AN 888: PHY Lite for Parallel Interface Reference Design with Dynamic Reconfiguration for Intel® Stratix® 10 Devices|
|Description||The PHY Lite reference design demonstrates the usage of dynamic reconfiguration feature using the PHY Lite for Parallel Interfaces Intel® Stratix® 10 FPGA IP cores. Two instances of PHY Lite for Parallel Interfaces Intel Stratix 10 FPGA IP cores are placed in different I/O tiles on a single FPGA. These PHY Lite instances are loopback|
using the HiLo loopback card. One PHY Lite instance is configured as a transmitter and the other PHY Lite instance is configured as a receiver.
|Development Kit||Stratix 10 GX FPGA Development Kit|
Note: After downloading the design example, you must prepare the design template. The file you downloaded is of the form of a <project>.par file which contains a compressed version of your design files (similar to a .qar file) and metadata describing the project. The combination of this information is what constitutes a <project>.par file. In releases 16.0 or newer, you can simply double click on the <project>.par file and Quartus will launch that project.
Browse to the <project>.par file you downloaded, click next, followed by Finish, and your design template will be installed and displayed in the Project Navigator pane in Quartus.
Note: When a design is stored in the Design Store as a design template, it has been previously regression tested against the stated version of Quartus software. The regression ensures the design template passes analysis/synthesis/fitting/assembly steps in the Quartus design flow.
At the command-line, type the following command:
Once the process completes, then type:
|Total Downloads||13 (From 13 Jun 2019 to 20 Sep 2019)|
|Quartus Prime Version||Download Quartus Prime v19.1|
|Quartus Prime Edition||Pro|
Last updated on June 13, 2019, 4:16 a.m.