Intel® Arria® 10 FPGA – AN 887: PHY Lite for Parallel Interface with Dynamic Reconfiguration for Intel Devices Reference Design

Intel® Arria® 10 FPGA – AN 887: PHY Lite for Parallel Interface with Dynamic Reconfiguration for Intel Devices Reference Design

714451
4/26/2019

Introduction

The PHY Lite for Parallel Interfaces Intel® FPGA IP core for Intel Arria® 10 FPGAs has a per-bit calibration capability that is used to calibrate each DQ pin delay to achieve maximum performance. When a large amount of DQ pins are used on a high-speed transfer, it is very likely that most have a narrower passing window. This limits the maximum performance of the system, as well as the possibility of data corruption.

Development Kit

Intel® Arria® 10 GX FPGA Development Kits

Design Details

Device Family

Intel® Arria® 10 FPGAs and SoC FPGAs
Quartus Edition

Intel® Quartus® Prime Pro Edition
Quartus Version

19.1
IP Cores (21)
IP Core IP Core Category
Altera PHYLite for memory TransceiverPHY
PHYLite Core Component for 20nm Families SerialLite
Top level generated instrumentation fabric Debug & Performance
Altera SignalTap II Agent Debug and Performance
PIO (Parallel I/O) Other
Avalon-MM Pipeline Bridge QsysInterconnect
On-Chip Memory (RAM or ROM) OnChipMemory
JTAG UART ConfigurationProgramming
Nios II Gen2 Processor NiosII
Nios II Gen2 Processor Unit NiosII
MM Interconnect QsysInterconnect
Memory-Mapped Multiplexer QsysInterconnect
Memory-Mapped Demultiplexer QsysInterconnect
Avalon-MM Master Translator QsysInterconnect
Avalon-MM Slave Translator QsysInterconnect
Avalon-MM Master Agent QsysInterconnect
Avalon-MM Slave Agent QsysInterconnect
Avalon-ST Single Clock FIFO QsysInterconnect
Memory-Mapped Router QsysInterconnect
IRQ Mapper QsysInterconnect
Reset Controller QsysInterconnect

Detailed Description

Prepare the design template in the Quartus Prime software GUI (version 14.1 and later)


Note: After downloading the design example, you must prepare the design template. The file you downloaded is of the form of a <project>.par file which contains a compressed version of your design files (similar to a .qar file) and metadata describing the project. The combination of this information is what constitutes a <project>.par file. In releases 16.0 or newer, you can simply double click on the <project>.par file and Quartus will launch that project.


The second means to bring up the project template is through the New Project Wizard (File -> New Project Wizard). After entering the project name and folder on the first panel, the second panel will ask you to specify an empty project or project template. Select project template. You will see a list of Design Templates projects that you have loaded prior as well as various "Baseline Pinout Designs" that contain the pinout and settings for a variety of development kits. If you don't see your design template in the list, click on the link that states install the Design Templates circled below:



Browse to the <project>.par file you downloaded, click next, followed by Finish, and your design template will be installed and displayed in the Project Navigator pane in Quartus.


Note: When a design is stored in the Design Store as a design template, it has been previously regression tested against the stated version of Quartus software. The regression ensures the design template passes analysis/synthesis/fitting/assembly steps in the Quartus design flow.



Prepare the design template in the Quartus Prime software command-line


At the command-line, type the following command:

quartus_sh --platform_install -package <project directory>/<project>.par


Once the process completes, then type:

quartus_sh --platform -name <project>



Note:

* ACDS Version: 19.1.0 Pro


Development Kit

Intel® Arria® 10 GX FPGA Development Kits

Design Details

Device Family

Intel® Arria® 10 FPGAs and SoC FPGAs
Quartus Edition

Intel® Quartus® Prime Pro Edition
Quartus Version

19.1