|Name||AN 887: PHY Lite for Parallel Interface Reference Design with Dynamic Reconfiguration for Intel® Arria® 10 Devices|
|Description||The PHY Lite for Parallel Interfaces Intel Arria 10 FPGA IP core has the per-bit|
calibration capability that is used to calibrate each DQ pin delay to achieve maximum
When a large amount of DQ pins are used on high-speed transfer, it is very likely that
most of the DQ have a narrower passing window. This limits the maximum
performance of the system, as well as having the possibility of data corruption.
|Development Kit||Arria 10 GX FPGA Development Kit|
Download (The download link will expire on March 6, 2021, 9:51 p.m., please refresh the page to get a new link.)
Note: After downloading the design example, you must prepare the design template. The file you downloaded is of the form of a <project>.par file which contains a compressed version of your design files (similar to a .qar file) and metadata describing the project. The combination of this information is what constitutes a <project>.par file. In releases 16.0 or newer, you can simply double click on the <project>.par file and Quartus will launch that project.
Browse to the <project>.par file you downloaded, click next, followed by Finish, and your design template will be installed and displayed in the Project Navigator pane in Quartus.
Note: When a design is stored in the Design Store as a design template, it has been previously regression tested against the stated version of Quartus software. The regression ensures the design template passes analysis/synthesis/fitting/assembly steps in the Quartus design flow.
At the command-line, type the following command:
Once the process completes, then type:
|Quartus Prime Version||Download Quartus Prime v19.1|
|Quartus Prime Edition||Pro|
Last updated on June 13, 2019, 3:48 a.m.