Design Store

Intel Arria 10 DisplayPort TX-only Design  

CategoryDesign Example
NameIntel Arria 10 DisplayPort TX-only Design
DescriptionThe Intel® Arria® 10 DisplayPort TX-only design demonstrates how the DisplayPort Intel FPGA IP source (TX) transmits 4Kp60 video output generated by the Test Pattern Generator II Intel FPGA IP. This design uses the Bitec FMC daughter card to transmit the video output.

The .par file contains '' and other design files. Unzip the '' and run '' script in Nios terminal to build the software prior design compilation.
Operating SystemBareMetal
IP Core
IP CoreHeading
Top level generated instrumentation fabricDebug & Performance
Altera Arria 10 XCVR Reset SequencerOther
Clocked Video Output II (4K Ready)AudioVideo
Video and Image Processing SuiteOther
Video Input BridgeAudioVideo
Test Pattern Generator II (4K Ready)Other
Nios II Gen2 ProcessorNiosII
Nios II Gen2 Processor UnitNiosII
Avalon FIFO MemoryOnChipMemory
Avalon-MM Pipeline BridgeQsysInterconnect
MM InterconnectQsysInterconnect
Avalon-MM Slave AgentQsysInterconnect
Avalon-ST Single Clock FIFOQsysInterconnect
Avalon-MM Slave TranslatorQsysInterconnect
Memory-Mapped DemultiplexerQsysInterconnect
Memory-Mapped MultiplexerQsysInterconnect
Avalon-ST Handshake Clock CrosserQsysInterconnect
Avalon-MM Master AgentQsysInterconnect
Memory-Mapped Traffic LimiterQsysInterconnect
Avalon-MM Master TranslatorQsysInterconnect
Memory-Mapped RouterQsysInterconnect
Reset ControllerQsysInterconnect
PIO (Parallel I/O)Other
IRQ MapperQsysInterconnect
JTAG UARTConfigurationProgramming
On-Chip Memory (RAM or ROM)OnChipMemory
Interval TimerPeripherals
System ID PeripheralOther
Arria 10 Transceiver Native PHYTransceiverPHY
Arria 10 FPLLClocksPLLsResets
Transceiver PHY Reset ControllerTransceiverPHY
Altera IOPLLClocksPLLsResets
FamilyArria 10
AN 883: Intel Arria 10 DisplayPort TX-only DesignThe Intel Arria 10 DisplayPort TX-only Design Application Note contains information such as quick start guide to run the design, how to create the design, design clocking scheme, design components and other design related information.
Development KitArria 10 GX FPGA Development Kit
Installation Package

Note: After downloading the design example, you must prepare the design template. The file you downloaded is of the form of a <project>.par file which contains a compressed version of your design files (similar to a .qar file) and metadata describing the project. The combination of this information is what constitutes a <project>.par file. In releases 16.0 or newer, you can simply double click on the <project>.par file and Quartus will launch that project.

The second means to bring up the project template is through the New Project Wizard (File -> New Project Wizard). After entering the project name and folder on the first panel, the second panel will ask you to specify an empty project or project template. Select project template. You will see a list of Design Templates projects that you have loaded prior as well as various "Baseline Pinout Designs" that contain the pinout and settings for a variety of development kits. If you don't see your design template in the list, click on the link that states install the Design Templates circled below:

Browse to the <project>.par file you downloaded, click next, followed by Finish, and your design template will be installed and displayed in the Project Navigator pane in Quartus.

Note: When a design is stored in the Design Store as a design template, it has been previously regression tested against the stated version of Quartus software. The regression ensures the design template passes analysis/synthesis/fitting/assembly steps in the Quartus design flow.

At the command-line, type the following command:

quartus_sh --platform_install –package <project directory>/A10_DP_TX_FMC_PRO.par

Once the process completes, then type:

quartus_sh --platform –name A10_DP_TX_FMC_PRO

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Quartus Prime VersionDownload Quartus Prime v18.1
Quartus Prime EditionPro

Last updated on April 9, 2019, 6:33 p.m.