|Name||Intel Cyclone 10 LP FPGA Triple-Speed Ethernet and Intel On-Board PHY Chip Reference Design|
|Description||The Intel® FPGA Triple-Speed Ethernet and Intel® on-board PHY chip reference design demonstrates Ethernet operation between the Triple-Speed Ethernet IP core and onboard Intel XWAY PHY11G Gigabit PHY chip in Intel Cyclone 10 LP FPGA Evaluation Kit.|
|Family||Cyclone 10 LP|
|Development Kit||Cyclone 10 LP FPGA Evaluation Kit|
Download (The download link will expire on June 23, 2021, 8:54 a.m., please refresh the page to get a new link.)
Note: After downloading the design example, you must prepare the design template. The file you downloaded is of the form of a <project>.par file which contains a compressed version of your design files (similar to a .qar file) and metadata describing the project. The combination of this information is what constitutes a <project>.par file. In releases 16.0 or newer, you can simply double click on the <project>.par file and Quartus will launch that project.
Browse to the <project>.par file you downloaded, click next, followed by Finish, and your design template will be installed and displayed in the Project Navigator pane in Quartus.
Note: When a design is stored in the Design Store as a design template, it has been previously regression tested against the stated version of Quartus software. The regression ensures the design template passes analysis/synthesis/fitting/assembly steps in the Quartus design flow.
At the command-line, type the following command:
Once the process completes, then type:
|Quartus Prime Version||Download Quartus Prime v18.0|
|Quartus Prime Edition||Standard|
Last updated on Dec. 5, 2018, 3:29 p.m.