Intel® Stratix® 10 FPGA – Ultra Low Latency Ethernet 10G for Intel Devices Reference Design

Intel® Stratix® 10 FPGA – Ultra Low Latency Ethernet 10G for Intel Devices Reference Design

715143
6/5/2018

Introduction

The Ultra Low Latency Ethernet 10G reference design demonstrates a low latency 10G Ethernet solution for Intel® Stratix® 10 devices. This reference design, which uses 10GBASE-R PHY with IEEE 1588v2 mode, is capable of achieving a lower round-trip latency of 171.0 ns compared to the 10GBASE-R Ethernet design example for Intel Stratix 10 devices with 246.5 ns.

Design Details

Device Family

Intel® Stratix® 10 TX FPGA

Quartus Edition

Intel® Quartus® Prime Pro Edition

Quartus Version

18.0

IP Cores (8)
IP Core IP Core Category
Top level generated instrumentation fabric Debug & Performance
Clock Source Clocks; PLLs and Resets
Avalon-MM Slave Translator QsysInterconnect
altera_jtag_avalon_master QsysInterconnect
Avalon-MM Master Translator QsysInterconnect
Avalon-ST Single Clock FIFO QsysInterconnect
Low Latency Ethernet 10G MAC Ethernet
Stratix 10 Transceiver PHY Reset Controller Transceiver PHY

Detailed Description

Prepare the design template in the Quartus Prime software GUI (version 14.1 and later)


Note: After downloading the design example, you must prepare the design template. The file you downloaded is of the form of a <project>.par file which contains a compressed version of your design files (similar to a .qar file) and metadata describing the project. The combination of this information is what constitutes a <project>.par file. In releases 16.0 or newer, you can simply double click on the <project>.par file and Quartus will launch that project.


The second means to bring up the project template is through the New Project Wizard (File -> New Project Wizard). After entering the project name and folder on the first panel, the second panel will ask you to specify an empty project or project template. Select project template. You will see a list of Design Templates projects that you have loaded prior as well as various "Baseline Pinout Designs" that contain the pinout and settings for a variety of development kits. If you don't see your design template in the list, click on the link that states install the Design Templates circled below:



Browse to the <project>.par file you downloaded, click next, followed by Finish, and your design template will be installed and displayed in the Project Navigator pane in Quartus.


Note: When a design is stored in the Design Store as a design template, it has been previously regression tested against the stated version of Quartus software. The regression ensures the design template passes analysis/synthesis/fitting/assembly steps in the Quartus design flow.



Prepare the design template in the Quartus Prime software command-line


At the command-line, type the following command:

quartus_sh --platform_install -package <project directory>/<project>.par


Once the process completes, then type:

quartus_sh --platform -name <project>

Design Details

Device Family

Intel® Stratix® 10 TX FPGA

Quartus Edition

Intel® Quartus® Prime Pro Edition

Quartus Version

18.0