Intel® Arria® 10 FPGA – PCIe* 3.0 x8 DMA Design Example

Intel® Arria® 10 FPGA – PCIe* 3.0 x8 DMA Design Example

714948
5/23/2018

Introduction

This design example includes a high-performance DMA with an Avalon® memory-mapped interface that connects to the PCI Express* hard IP core. It transfers data either between on-chip memory and system memory, or external memory and system memory. The reference design includes Linux* software drivers that set up the DMA transfer. You can also use the software driver to measure and display the performance achieved for the transfers. This reference design allows you to evaluate the performance of the PCI Express protocol using the Avalon memory-mapped interface.

Design Details

Device Family

Intel® Arria® 10 FPGAs and SoC FPGAs

Quartus Edition

Intel® Quartus® Prime Pro Edition

Quartus Version

18.0

IP Cores (32)
IP Core IP Core Category
Top level generated instrumentation fabric Debug & Performance
Arria 10 Hard IP for PCI Express PCIExpress
Arria 10 FPLL ClocksPLLsResets
Arria 10 Transceiver ATX PLL TransceiverPLL
Arria 10 Transceiver Native PHY TransceiverPHY
Arria 10 External Memory Interfaces ExternalMemoryInterfaces
EMIF Core Component for 20nm Families ExternalMemoryInterfaces
Avalon-MM Pipeline Bridge QsysInterconnect
On-Chip Memory (RAM or ROM) OnChipMemory
MM Interconnect QsysInterconnect
Avalon-MM Master Translator QsysInterconnect
Avalon-MM Slave Translator QsysInterconnect
Reset Controller QsysInterconnect
Arria 10 External Memory Interfaces Debug Component ExternalMemoryInterfaces
alt_mem_if JTAG to Avalon Master Bridge BridgesAndAdaptors
Avalon-ST Bytes to Packets Converter QsysInterconnect
Avalon-ST Channel Adapter QsysInterconnect
Avalon-ST Single Clock FIFO QsysInterconnect
Avalon-ST JTAG Interface QsysInterconnect
Avalon-ST Packets to Bytes Converter QsysInterconnect
Avalon-ST Timing Adapter QsysInterconnect
Avalon Packets to Transaction Converter QsysInterconnect
Avalon-ST Pipeline Stage QsysInterconnect
Avalon-ST Dual Clock FIFO QsysInterconnect
Memory-Mapped Demultiplexer QsysInterconnect
Memory-Mapped Multiplexer QsysInterconnect
Avalon-MM Master Agent QsysInterconnect
Memory-Mapped Width Adapter QsysInterconnect
Memory-Mapped Traffic Limiter QsysInterconnect
Avalon-MM Slave Agent QsysInterconnect
Memory-Mapped Burst Adapter QsysInterconnect
Memory-Mapped Router QsysInterconnect

Detailed Description

Prepare the design template in the Quartus Prime software GUI (version 14.1 and later)


Note: After downloading the design example, you must prepare the design template. The file you downloaded is of the form of a <project>.par file which contains a compressed version of your design files (similar to a .qar file) and metadata describing the project. The combination of this information is what constitutes a <project>.par file. In releases 16.0 or newer, you can simply double click on the <project>.par file and Quartus will launch that project.


The second means to bring up the project template is through the New Project Wizard (File -> New Project Wizard). After entering the project name and folder on the first panel, the second panel will ask you to specify an empty project or project template. Select project template. You will see a list of Design Templates projects that you have loaded prior as well as various "Baseline Pinout Designs" that contain the pinout and settings for a variety of development kits. If you don't see your design template in the list, click on the link that states install the Design Templates circled below:



Browse to the <project>.par file you downloaded, click next, followed by Finish, and your design template will be installed and displayed in the Project Navigator pane in Quartus.


Note: When a design is stored in the Design Store as a design template, it has been previously regression tested against the stated version of Quartus software. The regression ensures the design template passes analysis/synthesis/fitting/assembly steps in the Quartus design flow.



Prepare the design template in the Quartus Prime software command-line


At the command-line, type the following command:

quartus_sh --platform_install -package <project directory>/<project>.par


Once the process completes, then type:

quartus_sh --platform -name <project>



Note:

* ACDS Version: 18.0.0 Pro


Design Details

Device Family

Intel® Arria® 10 FPGAs and SoC FPGAs

Quartus Edition

Intel® Quartus® Prime Pro Edition

Quartus Version

18.0