Intel® Cyclone® 10 GX FPGA – Intel DisplayPort 4Kp60 with Video and Image Processing Pipeline Retransmit Reference Design

Intel® Cyclone® 10 GX FPGA – Intel DisplayPort 4Kp60 with Video and Image Processing Pipeline Retransmit Reference Design

714774
8/13/2018

Introduction

This reference design demonstrates Intel's video connectivity, and the DisplayPort Sink (RX) and Source (TX) functions using a video loop-through system.

Design Details

Device Family

Intel® Cyclone® 10 GX FPGA

Quartus Edition

Intel® Quartus® Prime Pro Edition

Quartus Version

18.0

IP Cores (49)
IP Core IP Core Category
Top level generated instrumentation fabric Debug & Performance
Altera Arria 10 XCVR Reset Sequencer Other
Altera SignalTap II Agent Debug and Performance
Altera IOPLL ClocksPLLsResets
Nios II Gen2 Processor NiosII
Nios II Gen2 Processor Unit NiosII
Avalon FIFO Memory OnChipMemory
Avalon-MM Pipeline Bridge QsysInterconnect
DisplayPort AudioVideo
MM Interconnect QsysInterconnect
Avalon-MM Slave Agent QsysInterconnect
Avalon-ST Single Clock FIFO QsysInterconnect
Avalon-MM Slave Translator QsysInterconnect
Memory-Mapped Demultiplexer QsysInterconnect
Memory-Mapped Multiplexer QsysInterconnect
Avalon-ST Handshake Clock Crosser QsysInterconnect
Avalon-MM Master Agent QsysInterconnect
Memory-Mapped Traffic Limiter QsysInterconnect
Avalon-MM Master Translator QsysInterconnect
Memory-Mapped Router QsysInterconnect
PIO (Parallel I/O) Other
Reset Controller QsysInterconnect
IRQ Mapper QsysInterconnect
JTAG UART ConfigurationProgramming
altera_jtag_avalon_master QsysInterconnect
Avalon-ST Bytes to Packets Converter QsysInterconnect
Avalon-ST Channel Adapter QsysInterconnect
Avalon-ST JTAG Interface QsysInterconnect
Avalon-ST Packets to Bytes Converter QsysInterconnect
Avalon-ST Timing Adapter QsysInterconnect
Avalon Packets to Transaction Converter QsysInterconnect
On-Chip Memory (RAM or ROM) OnChipMemory
Interval Timer Peripherals
System ID Peripheral Other
Clocked Video Input II (4K Ready) AudioVideo
Video and Image Processing Suite Other
Clocked Video Output II (4K Ready) AudioVideo
Video Input Bridge AudioVideo
EMIF Core Component for 20nm Families ExternalMemoryInterfaces
EMIF Error Correction Code (ECC) Component Internal Components
EMIF Error Correction Code (ECC) Component for Arria 10 Internal Components
Mixer II (4K Ready) AudioVideo
Avalon-ST Pipeline Stage QsysInterconnect
Memory-Mapped Burst Adapter QsysInterconnect
Memory-Mapped Width Adapter QsysInterconnect
Frame Buffer II (4K Ready) AudioVideo
Arria 10 Transceiver Native PHY TransceiverPHY
Transceiver PHY Reset Controller TransceiverPHY
Arria 10 FPLL ClocksPLLsResets

Detailed Description

Prepare the design template in the Quartus Prime software GUI (version 14.1 and later)


Note: After downloading the design example, you must prepare the design template. The file you downloaded is of the form of a <project>.par file which contains a compressed version of your design files (similar to a .qar file) and metadata describing the project. The combination of this information is what constitutes a <project>.par file. In releases 16.0 or newer, you can simply double click on the <project>.par file and Quartus will launch that project.


The second means to bring up the project template is through the New Project Wizard (File -> New Project Wizard). After entering the project name and folder on the first panel, the second panel will ask you to specify an empty project or project template. Select project template. You will see a list of Design Templates projects that you have loaded prior as well as various "Baseline Pinout Designs" that contain the pinout and settings for a variety of development kits. If you don't see your design template in the list, click on the link that states install the Design Templates circled below:



Browse to the <project>.par file you downloaded, click next, followed by Finish, and your design template will be installed and displayed in the Project Navigator pane in Quartus.


Note: When a design is stored in the Design Store as a design template, it has been previously regression tested against the stated version of Quartus software. The regression ensures the design template passes analysis/synthesis/fitting/assembly steps in the Quartus design flow.



Prepare the design template in the Quartus Prime software command-line


At the command-line, type the following command:

quartus_sh --platform_install -package <project directory>/<project>.par


Once the process completes, then type:

quartus_sh --platform -name <project>


Design Details

Device Family

Intel® Cyclone® 10 GX FPGA

Quartus Edition

Intel® Quartus® Prime Pro Edition

Quartus Version

18.0