Intel® Stratix® 10 FPGA – FIFO vs. FIFO2 Simulation Design Example

Intel® Stratix® 10 FPGA – FIFO vs. FIFO2 Simulation Design Example

714683
7/29/2018

Introduction

Intel® Stratix® 10 FPGAs offer two FIFO IP options – FIFO and FIFO2. FIFO is identical in other device families while FIFO2 is specifically designed with the Intel HyperFlex™ architecture in mind, targeted for high-speed designs. Please refer to the Intel Stratix 10 Embedded Memory User Guide for the FIFO2 specification. Due to its pipelined structure, FIFO2 has a different latency compared to FIFO. This design shows the difference between FIFO and FIFO2 in the reset scheme and read/write operations. - No development kit required - Use the Intel Quartus® Prime Software Version 18.0 and ModelSim* - The package contains a project that includes the source files: a top-level RTL, a testbench file, and a sim_top.tcl file to be sourced in ModelSim to run the simulation

Design Details

Device Family

Intel® Stratix® 10 FPGAs and SoC FPGAs

Quartus Edition

Intel® Quartus® Prime Pro Edition

Quartus Version

18.0

IP Cores (1)
IP Core IP Core Category
FIFO OnChipMemory

Detailed Description

Prepare the design template in the Quartus Prime software GUI (version 14.1 and later)


Note: After downloading the design example, you must prepare the design template. The file you downloaded is of the form of a <project>.par file which contains a compressed version of your design files (similar to a .qar file) and metadata describing the project. The combination of this information is what constitutes a <project>.par file. In releases 16.0 or newer, you can simply double click on the <project>.par file and Quartus will launch that project.


The second means to bring up the project template is through the New Project Wizard (File -> New Project Wizard). After entering the project name and folder on the first panel, the second panel will ask you to specify an empty project or project template. Select project template. You will see a list of Design Templates projects that you have loaded prior as well as various "Baseline Pinout Designs" that contain the pinout and settings for a variety of development kits. If you don't see your design template in the list, click on the link that states install the Design Templates circled below:



Browse to the <project>.par file you downloaded, click next, followed by Finish, and your design template will be installed and displayed in the Project Navigator pane in Quartus.


Note: When a design is stored in the Design Store as a design template, it has been previously regression tested against the stated version of Quartus software. The regression ensures the design template passes analysis/synthesis/fitting/assembly steps in the Quartus design flow.



Prepare the design template in the Quartus Prime software command-line


At the command-line, type the following command:

quartus_sh --platform_install -package <project directory>/<project>.par


Once the process completes, then type:

quartus_sh --platform -name <project>



Note:

* ACDS Version: 18.0.0 Pro


Design Details

Device Family

Intel® Stratix® 10 FPGAs and SoC FPGAs

Quartus Edition

Intel® Quartus® Prime Pro Edition

Quartus Version

18.0