Design Store


Boot from EPCQ (Serial Flash) example  


CategoryDesign Example
NameBoot from EPCQ (Serial Flash) example
DescriptionThis simple reference design demonstrates how to boot from EPCQ memory decive on Intel's Cyclone 10LP evaluation board.

It is based on S/Labs HBMC IP and Intel's Serial Flash controller.

This tutorial describes key aspects of a pre-configured .qsys reference project and then walks through the process of generating and compiling that .Qsys project. This tutorial then describes how to compile the example Nios II source code, download the firmware into the EPCQ memory device and then run the reference design on the development board.

This reference design was submitted in September 2017 and is being actively maintained by Synaptic Laboratories Ltd (S/Labs). Please ignore the word "Legacy" in the category field.

This reference design can be easily modified for other development boards and other Intel FPGA families.

Updated on 20 July 2018 to include Free Trial IP.
Operating SystemNone
IP Core
IP CoreHeading
Version1.0
FamilyCyclone 10 LP
Device10CL025
Documentation
DocumentDescription
Tutorial 004A: Boot from EPCQ (Serial Flash) This tutorial describes key aspects of a pre-configured .qsys reference project, how to compile the example Nios II source code, download the firmware into the EPCQ memory device and then run the reference design on the development board.
Tutorial 004B: Secure Boot from EPCQ (Serial Flash)This tutorial is based on the Intel Cyclone 10 LP FPGA board and describes the process of adding S/Labs Secure Flash memory IP to automatically encrypt/decrypt firmware and user data. Before proceeding to the Secure Boot From Encrypted Firmware Lab, please follow the tutorial descibed above : Tutorial 004A: Boot from EPCQ (Serial Flash)
The License and Confidentiality AgreementBy downloading and using SLL's HBMC IP you are accepting and agreeing to the terms and conditions contained in this Agreement
Free Trial HBMC IPA Free Trial Bundle that contains S/Labs HBMC IP v3.1.1 for Intel FPGA. No registration required. Includes a Free License Credential issued to You for the Full Edition of the HBMC IP. This Credential: (a) includes a free License Key that You need to install into Quartus Prime; (b) has no expiration date; (c) permits 10 minutes of runtime; (d) permits the use of an unlimited number of concurrent developer seats; (e) works with any Network Interface Card (NIC) Identifier.
HyperRAM EPCQ Reference ProjectThis reference design helps the designer to employ S/Labs HBMC IP and Intel's Serial Flash controller in a typical Quartus project. This .zip file will be automatically downloaded by your browser to your file system. Please download the Free Trial of the HBMC IP with 10 minute runtimes from the links above. Once downloaded, we suggest that you follow Tutorial004A: Boot from EPCQ (Serial Flash) example
Synaptic Laboratories Limited website (URL)This is a URL link to Synaptic Laboratories Limited website.
S/Labs HBMC IP design guidelinesThis document outlines the basic design guidelines for using S/Labs Hyperbus memory controller IP.
Development KitCyclone 10 LP FPGA Evaluation Kit
Installation Package

Note: After downloading the design example, you must prepare the design template. The file you downloaded is of the form of a <project>.par file which contains a compressed version of your design files (similar to a .qar file) and metadata describing the project. The combination of this information is what constitutes a <project>.par file. In releases 16.0 or newer, you can simply double click on the <project>.par file and Quartus will launch that project.

The second means to bring up the project template is through the New Project Wizard (File -> New Project Wizard). After entering the project name and folder on the first panel, the second panel will ask you to specify an empty project or project template. Select project template. You will see a list of Design Templates projects that you have loaded prior as well as various "Baseline Pinout Designs" that contain the pinout and settings for a variety of development kits. If you don't see your design template in the list, click on the link that states install the Design Templates circled below:


Browse to the <project>.par file you downloaded, click next, followed by Finish, and your design template will be installed and displayed in the Project Navigator pane in Quartus.

Note: When a design is stored in the Design Store as a design template, it has been previously regression tested against the stated version of Quartus software. The regression ensures the design template passes analysis/synthesis/fitting/assembly steps in the Quartus design flow.

At the command-line, type the following command:

quartus_sh --platform_install –package <project directory>/HyperRAM_EPCQ_Project_c10lp.par

Once the process completes, then type:

quartus_sh --platform –name HyperRAM_EPCQ_Project_c10lp

Download   (The download link will expire on Dec. 5, 2021, 10:37 a.m., please refresh the page to get a new link.)
Quartus Prime VersionDownload Quartus Prime v17.1
Quartus Prime EditionStandard
VendorSynaptic Laboratories Ltd.


Last updated on July 25, 2018, 5:29 p.m.