Design Store


RapidIO II Reference Design for Avalon-ST Pass-Through Interface  


CategoryDevelopment Kit
NameRapidIO II Reference Design for Avalon-ST Pass-Through Interface
DescriptionAN836: RapidIO II Reference Design for Avalon-ST Pass-Through Interface
Operating SystemNone
IP Core
IP CoreHeading
Top level generated instrumentation fabricDebug & Performance
Altera SignalTap II AgentDebug and Performance
JTAG Debug Link (internal module)ConfigurationProgramming
Avalon-ST Bytes to Packets ConverterQsysInterconnect
Avalon-ST Single Clock FIFOQsysInterconnect
Avalon-ST Timing AdapterQsysInterconnect
Avalon-ST JTAG InterfaceQsysInterconnect
Avalon-ST Packets to Bytes ConverterQsysInterconnect
Avalon MM Debug FabricQsysInterconnect
MM InterconnectQsysInterconnect
Avalon-ST AdapterQsysInterconnect
Avalon-ST Error AdapterQsysInterconnect
Avalon-MM Slave AgentQsysInterconnect
Avalon-MM Slave TranslatorQsysInterconnect
Memory-Mapped DemultiplexerQsysInterconnect
Memory-Mapped MultiplexerQsysInterconnect
Memory-Mapped RouterQsysInterconnect
Avalon-MM Master AgentQsysInterconnect
Memory-Mapped Traffic LimiterQsysInterconnect
Avalon-MM Master TranslatorQsysInterconnect
Trace ROMQsysInterconnect
Avalon Packets to Transaction ConverterQsysInterconnect
Avalon ST Debug FabricQsysInterconnect
Avalon-ST DemultiplexerQsysInterconnect
Avalon-ST Channel AdapterQsysInterconnect
Altera Management Reset BlockOther
Reset ControllerQsysInterconnect
Avalon-ST MultiplexerQsysInterconnect
altera_jtag_avalon_masterQsysInterconnect
Avalon-MM Pipeline BridgeQsysInterconnect
Avalon-MM Clock Crossing BridgeQsysInterconnect
RapidIO II (IDLE2 up to 6.25 Gbaud)RapidIO
Stratix 10 Transceiver Native PHYTransceiver PHY
Stratix 10 Transceiver PHY Reset ControllerTransceiver PHY
Version1.0
FamilyStratix 10
Device1SG280L_ES
Documentation
DocumentDescription
AN 836: RapidIO II Reference Design for Avalon-ST Pass-Through Interface-
Development KitStratix 10 GX L-Tile Development Kit
Installation Package

Note: After downloading the design example, you must prepare the design template. The file you downloaded is of the form of a <project>.par file which contains a compressed version of your design files (similar to a .qar file) and metadata describing the project. The combination of this information is what constitutes a <project>.par file. In releases 16.0 or newer, you can simply double click on the <project>.par file and Quartus will launch that project.

The second means to bring up the project template is through the New Project Wizard (File -> New Project Wizard). After entering the project name and folder on the first panel, the second panel will ask you to specify an empty project or project template. Select project template. You will see a list of Design Templates projects that you have loaded prior as well as various "Baseline Pinout Designs" that contain the pinout and settings for a variety of development kits. If you don't see your design template in the list, click on the link that states install the Design Templates circled below:


Browse to the <project>.par file you downloaded, click next, followed by Finish, and your design template will be installed and displayed in the Project Navigator pane in Quartus.

Note: When a design is stored in the Design Store as a design template, it has been previously regression tested against the stated version of Quartus software. The regression ensures the design template passes analysis/synthesis/fitting/assembly steps in the Quartus design flow.

At the command-line, type the following command:

quartus_sh --platform_install –package <project directory>/srio2_s10_avst_6g_de.par

Once the process completes, then type:

quartus_sh --platform –name srio2_s10_avst_6g_de

Download   (The download link will expire on Sept. 20, 2021, 11:43 p.m., please refresh the page to get a new link.)
Quartus Prime VersionDownload Quartus Prime v17.1
Quartus Prime EditionPro
VendorIntel


Last updated on Feb. 4, 2021, 9:36 p.m.