Design Store

Intel® Stratix 10® GX 16-Lane RX JESD204B-ADC12DJ3200 Interoperability Reference Design   

CategoryDesign Example
NameIntel® Stratix 10® GX 16-Lane RX JESD204B-ADC12DJ3200 Interoperability Reference Design
DescriptionThis application note showcases the synchronization of two x8-lane Intel Stratix 10 FPGA JESD204B RX IP Cores to interoperate with the latest 12-bit, 16-lane TI ADC12DJ3200 Evaluation Module (EVM) running at 6.4Gbps per lane connected through FMC+ port A connector.
Operating SystemNone
IP Core
IP CoreHeading
FamilyStratix 10
AN833: Intel Stratix 10 GX 16-Lane JESD204B-ADC12DJ3200 Interoperability Reference DesignApplication Note for Intel Stratix 10 GX 16-Lane JESD204B-ADC12DJ3200 Interoperability Reference Design
Development KitStratix 10 Transceiver Signal Integrity Development Kit
Installation Package

Note: After downloading the design example, you must prepare the design template. The file you downloaded is of the form of a <project>.par file which contains a compressed version of your design files (similar to a .qar file) and metadata describing the project. The combination of this information is what constitutes a <project>.par file. In releases 16.0 or newer, you can simply double click on the <project>.par file and Quartus will launch that project.

The second means to bring up the project template is through the New Project Wizard (File -> New Project Wizard). After entering the project name and folder on the first panel, the second panel will ask you to specify an empty project or project template. Select project template. You will see a list of Design Templates projects that you have loaded prior as well as various "Baseline Pinout Designs" that contain the pinout and settings for a variety of development kits. If you don't see your design template in the list, click on the link that states install the Design Templates circled below:

Browse to the <project>.par file you downloaded, click next, followed by Finish, and your design template will be installed and displayed in the Project Navigator pane in Quartus.

Note: When a design is stored in the Design Store as a design template, it has been previously regression tested against the stated version of Quartus software. The regression ensures the design template passes analysis/synthesis/fitting/assembly steps in the Quartus design flow.

At the command-line, type the following command:

quartus_sh --platform_install –package <project directory>/s10hes_jesd204b_adc12dj3200_lmf888.par

Once the process completes, then type:

quartus_sh --platform –name s10hes_jesd204b_adc12dj3200_lmf888

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Last updated on June 22, 2018, 2:11 a.m.