|Name||Intel® Stratix 10® GX 16-Lane RX JESD204B-ADC12DJ3200 Interoperability Reference Design|
|Description||This application note showcases the synchronization of two x8-lane Intel Stratix 10 FPGA JESD204B RX IP Cores to interoperate with the latest 12-bit, 16-lane TI ADC12DJ3200 Evaluation Module (EVM) running at 6.4Gbps per lane connected through FMC+ port A connector.|
|Development Kit||Stratix 10 Transceiver Signal Integrity Development Kit|
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Note: After downloading the design example, you must prepare the design template. The file you downloaded is of the form of a <project>.par file which contains a compressed version of your design files (similar to a .qar file) and metadata describing the project. The combination of this information is what constitutes a <project>.par file. In releases 16.0 or newer, you can simply double click on the <project>.par file and Quartus will launch that project.
Browse to the <project>.par file you downloaded, click next, followed by Finish, and your design template will be installed and displayed in the Project Navigator pane in Quartus.
Note: When a design is stored in the Design Store as a design template, it has been previously regression tested against the stated version of Quartus software. The regression ensures the design template passes analysis/synthesis/fitting/assembly steps in the Quartus design flow.
At the command-line, type the following command:
Once the process completes, then type:
|Quartus Prime Version||Download Quartus Prime v17.1|
|Quartus Prime Edition||Pro|
Last updated on June 22, 2018, 2:11 a.m.