Design Store

AN803: Implementing Synchronized ADC-Arria 10 Multi-Link Design with JESD204B RX IP Core  

CategoryDesign Example
NameAN803: Implementing Synchronized ADC-Arria 10 Multi-Link Design with JESD204B RX IP Core
DescriptionThis design example contains sample files of the AN803 synchronized ADC-Arria 10 multi-link design for synthesis and simulation.
Operating SystemNone
IP Core
IP CoreHeading
Top level generated instrumentation fabricDebug & Performance
Altera Arria 10 XCVR Reset SequencerOther
Jesd204bJESD204B
Jesd204b PHY wrapperJESD204B
Arria 10 Transceiver Native PHYTransceiverPHY
Avalon-MM Pipeline BridgeQsysInterconnect
MM InterconnectQsysInterconnect
Avalon-MM Slave AgentQsysInterconnect
Avalon-ST Single Clock FIFOQsysInterconnect
Avalon-MM Slave TranslatorQsysInterconnect
Avalon-ST AdapterQsysInterconnect
Avalon-ST Error AdapterQsysInterconnect
Memory-Mapped DemultiplexerQsysInterconnect
Memory-Mapped MultiplexerQsysInterconnect
Avalon-MM Master AgentQsysInterconnect
Memory-Mapped Traffic LimiterQsysInterconnect
Avalon-MM Master TranslatorQsysInterconnect
Memory-Mapped Burst AdapterQsysInterconnect
Memory-Mapped RouterQsysInterconnect
Reset SequencerQsysInterconnect
Reset ControllerQsysInterconnect
Transceiver PHY Reset ControllerTransceiverPHY
Altera IOPLLClocksPLLsResets
altera_jtag_avalon_masterQsysInterconnect
Avalon-ST Bytes to Packets ConverterQsysInterconnect
Avalon-ST Channel AdapterQsysInterconnect
Avalon-ST JTAG InterfaceQsysInterconnect
Avalon-ST Packets to Bytes ConverterQsysInterconnect
Avalon-ST Timing AdapterQsysInterconnect
Avalon Packets to Transaction ConverterQsysInterconnect
PIO (Parallel I/O)Other
SPI (3 Wire Serial)SPI
Altera GPIOOther
Altera GPIO CoreOther
Version1.1
FamilyArria 10
Device10AS016
Documentation
DocumentDescription
AN803: Implementing Synchronized ADC-Arria 10 Multi-Link Design with JESD204B RX IP Core-
Development KitNon kit specific Arria 10 Design Examples
Installation Package

Note: After downloading the design example, you must prepare the design template. The file you downloaded is of the form of a <project>.par file which contains a compressed version of your design files (similar to a .qar file) and metadata describing the project. The combination of this information is what constitutes a <project>.par file. In releases 16.0 or newer, you can simply double click on the <project>.par file and Quartus will launch that project.

The second means to bring up the project template is through the New Project Wizard (File -> New Project Wizard). After entering the project name and folder on the first panel, the second panel will ask you to specify an empty project or project template. Select project template. You will see a list of Design Templates projects that you have loaded prior as well as various "Baseline Pinout Designs" that contain the pinout and settings for a variety of development kits. If you don't see your design template in the list, click on the link that states install the Design Templates circled below:


Browse to the <project>.par file you downloaded, click next, followed by Finish, and your design template will be installed and displayed in the Project Navigator pane in Quartus.

Note: When a design is stored in the Design Store as a design template, it has been previously regression tested against the stated version of Quartus software. The regression ensures the design template passes analysis/synthesis/fitting/assembly steps in the Quartus design flow.

At the command-line, type the following command:

quartus_sh --platform_install –package <project directory>/a10_jesd204b_RX_multilink_sync.par

Once the process completes, then type:

quartus_sh --platform –name a10_jesd204b_RX_multilink_sync

Download
Total Downloads62 (From 12 Feb 2018 to 13 Jul 2019)
Quartus Prime VersionDownload Quartus Prime v17.1
Quartus Prime EditionPro
VendorIntel


Last updated on Nov. 26, 2018, 2:55 p.m.