Design Store


PCIe AVMM DMA Gen2x4 On-Chip and External Memory  


CategoryDesign Example
NamePCIe AVMM DMA Gen2x4 On-Chip and External Memory
DescriptionFeatures:
Fast and easy to develop high performance PCIe Gen2x4 hardware
Example system is in the attached Quartus archive, which provides a pre-configured Qsys system
Includes 64-bit Windows and Linux driver and application that works with the example design
Software included has several test patterns for use of both forms of memory simultaneously or individually

Requirements:
QuartusII 17.0.0
Altera Cyclone V GT Development Kit
Example Design
A system with either 32-bit or 64-bit Linux or 64-bit Windows 7 installed
Operating SystemNone
IP Core
IP CoreHeading
Transceiver Reconfiguration ControllerTransceiverPHY
DDR3 SDRAM Controller with UniPHYExternalMemoryInterfaces
Altera DDR3 Hard Memory ControllerExternalMemoryInterfaces
External Memory DLL blockExternalMemoryInterfaces
altera_jtag_avalon_masterQsysInterconnect
Avalon-ST Bytes to Packets ConverterQsysInterconnect
Avalon-ST Channel AdapterQsysInterconnect
Avalon-ST Single Clock FIFOQsysInterconnect
Avalon-ST JTAG InterfaceQsysInterconnect
Avalon-ST Packets to Bytes ConverterQsysInterconnect
Reset ControllerQsysInterconnect
Avalon-ST Timing AdapterQsysInterconnect
Avalon Packets to Transaction ConverterQsysInterconnect
MM InterconnectQsysInterconnect
Avalon-MM Master TranslatorQsysInterconnect
Avalon-MM Slave TranslatorQsysInterconnect
Avalon-ST AdapterQsysInterconnect
Avalon-ST Error AdapterQsysInterconnect
Avalon-MM Slave AgentQsysInterconnect
Memory-Mapped Burst AdapterQsysInterconnect
Memory-Mapped Width AdapterQsysInterconnect
Memory-Mapped DemultiplexerQsysInterconnect
Memory-Mapped MultiplexerQsysInterconnect
Avalon-MM Master AgentQsysInterconnect
Memory-Mapped Traffic LimiterQsysInterconnect
Memory-Mapped RouterQsysInterconnect
External Memory OCT blockExternalMemoryInterfaces
DDR3 SDRAM External Memory Hard PHY CoreExternalMemoryInterfaces
DDR3 SDRAM External Memory PLL/DLL/OCT blockExternalMemoryInterfaces
DDR3 SDRAM Qsys SequencerExternalMemoryInterfaces
Avalon-ST Pipeline StageQsysInterconnect
Avalon-ST Dual Clock FIFOQsysInterconnect
On-Chip Memory (RAM or ROM)OnChipMemory
V-Series Avalon-MM DMA for PCI ExpressQsysInterconnect
Version1.0
FamilyCyclone V
Device5CGTFD9
Documentation
DocumentDescription
Test Software and Driver, Single Memory Type-LinuxSoftware allows testing of either On-Chip Memory or External Memory depending on which address is specified. Driver is included
Test Software and Driver, Single Memory Type-Windows x64Software allows testing of either On-Chip Memory or External Memory depending on which address is specified. Driver is included
Development KitCyclone V GT FPGA Development Kit
Installation Package

Note: After downloading the design example, you must prepare the design template. The file you downloaded is of the form of a <project>.par file which contains a compressed version of your design files (similar to a .qar file) and metadata describing the project. The combination of this information is what constitutes a <project>.par file. In releases 16.0 or newer, you can simply double click on the <project>.par file and Quartus will launch that project.

The second means to bring up the project template is through the New Project Wizard (File -> New Project Wizard). After entering the project name and folder on the first panel, the second panel will ask you to specify an empty project or project template. Select project template. You will see a list of Design Templates projects that you have loaded prior as well as various "Baseline Pinout Designs" that contain the pinout and settings for a variety of development kits. If you don't see your design template in the list, click on the link that states install the Design Templates circled below:


Browse to the <project>.par file you downloaded, click next, followed by Finish, and your design template will be installed and displayed in the Project Navigator pane in Quartus.

Note: When a design is stored in the Design Store as a design template, it has been previously regression tested against the stated version of Quartus software. The regression ensures the design template passes analysis/synthesis/fitting/assembly steps in the Quartus design flow.

At the command-line, type the following command:

quartus_sh --platform_install –package <project directory>/c5gt_gen2x4_ddr3.par

Once the process completes, then type:

quartus_sh --platform –name c5gt_gen2x4_ddr3

Download   (The download link will expire on Oct. 22, 2021, 1:51 a.m., please refresh the page to get a new link.)
Quartus Prime VersionDownload Quartus Prime v17.0
Quartus Prime EditionStandard
VendorIntel


Last updated on May 29, 2020, 10:57 a.m.