Design Store

Multi-Core NIOS II Processors Reference Design Based on Arria 10 SOC Development Board  

CategoryDesign Example
NameMulti-Core NIOS II Processors Reference Design Based on Arria 10 SOC Development Board
DescriptionThis design demonstrates the features of the Intel® Nios® II processor and Qsys system integration tool that are useful for creating systems with multiple processors. This short abstract provides some details on a reference design objectives and architecture. Using Qsys, we build a multiprocessor system containing four processors. Each processor is in a subsystem, creating a hierarchy with four subsystems with a separate memory map, coordinated with pipeline bridges.
Multiprocessor systems possess the benefit of increased performance, but nearly always at the price of significantly increased system complexity for both hardware and software. The idea of using multiple processors to perform different tasks and functions on different processors in real-time embedded applications is gaining popularity. Intel FPGAs provide an ideal platform for developing embedded multiprocessor systems, since the hardware can easily be modified and tuned using Qsys tool to provide optimal system performance. Increases in the size of FPGAs make possible system designs with many Nios II processors on a single chip. Furthermore, with a powerful integration tool like Qsys, different system configurations can be designed, built, and evaluated very quickly. Qsys enables hierarchical designs, reducing system complexity through compartmentalization of the design into discrete subsystems. Each subsystem exports user-defined interfaces, linking the subsystem hierarchy together.
Operating SystemBareMetal
IP Core
IP CoreHeading
PIO (Parallel I/O)Other
Nios II Gen2 ProcessorNiosII
Nios II Gen2 Processor UnitNiosII
IRQ MapperQsysInterconnect
IRQ Clock CrosserQsysInterconnect
MM InterconnectQsysInterconnect
Avalon-ST AdapterQsysInterconnect
Avalon-ST Error AdapterQsysInterconnect
Memory-Mapped DemultiplexerQsysInterconnect
Memory-Mapped MultiplexerQsysInterconnect
Avalon-ST Handshake Clock CrosserQsysInterconnect
Avalon-MM Slave AgentQsysInterconnect
Avalon-ST Single Clock FIFOQsysInterconnect
Avalon-MM Slave TranslatorQsysInterconnect
Avalon-MM Master AgentQsysInterconnect
Avalon-MM Master TranslatorQsysInterconnect
Memory-Mapped Burst AdapterQsysInterconnect
Memory-Mapped RouterQsysInterconnect
Altera Avalon MutexQsysInterconnect
Altera Serial Flash ControllerFlash
Altera ASMI ParallelConfigurationProgramming
Altera EPCQ Serial Flash controller coreConfigurationProgramming
JTAG UARTConfigurationProgramming
On-Chip Memory (RAM or ROM)OnChipMemory
Reset ControllerQsysInterconnect
System ID PeripheralOther
Interval TimerPeripherals
Altera IOPLLClocksPLLsResets
FamilyArria 10
Design Tutorial-
Development KitArria 10 SoC Development Kit
Installation Package

Note: After downloading the design example, you must prepare the design template. The file you downloaded is of the form of a <project>.par file which contains a compressed version of your design files (similar to a .qar file) and metadata describing the project. The combination of this information is what constitutes a <project>.par file. In releases 16.0 or newer, you can simply double click on the <project>.par file and Quartus will launch that project.

The second means to bring up the project template is through the New Project Wizard (File -> New Project Wizard). After entering the project name and folder on the first panel, the second panel will ask you to specify an empty project or project template. Select project template. You will see a list of Design Templates projects that you have loaded prior as well as various "Baseline Pinout Designs" that contain the pinout and settings for a variety of development kits. If you don't see your design template in the list, click on the link that states install the Design Templates circled below:

Browse to the <project>.par file you downloaded, click next, followed by Finish, and your design template will be installed and displayed in the Project Navigator pane in Quartus.

Note: When a design is stored in the Design Store as a design template, it has been previously regression tested against the stated version of Quartus software. The regression ensures the design template passes analysis/synthesis/fitting/assembly steps in the Quartus design flow.

At the command-line, type the following command:

quartus_sh --platform_install –package <project directory>/MULTICORE_SYSTEM.par

Once the process completes, then type:

quartus_sh --platform –name MULTICORE_SYSTEM

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Last updated on June 22, 2018, 2:11 a.m.