Design Store


HDMI Tx-Only VIP Suite Design for Arria 10  


CategoryDesign Example
NameHDMI Tx-Only VIP Suite Design for Arria 10
DescriptionThis reference design demonstrates the Intel FPGA High Definition Multimedia Interface (HDMI) 2.0 video connectivity IP core with a video processing pipeline based on IP cores from the Intel FPGA Video and Image Processing (VIP) Suite. This design is intended as a simple reference for interconnectivity between the HDMI IP core and the VIP Suite. This design demonstrates a simple configuration via a Nios II processor of a programmable oscillator on the Arria 10 GX FPGA Development Kit to drive the TX IOPLL and fPLL reference clocks.
Operating SystemNone
IP Core
IP CoreHeading
Altera Arria 10 XCVR Reset SequencerOther
Altera IOPLLClocksPLLsResets
Reset ControllerQsysInterconnect
Arria 10 FPLLClocksPLLsResets
Arria 10 Transceiver Native PHYTransceiverPHY
Transceiver PHY Reset ControllerTransceiverPHY
Altera HDMIAudioVideo
Altera PLL ReconfigClocksPLLsResets
PIO (Parallel I/O)Other
Nios II Gen2 ProcessorNiosII
Nios II Gen2 Processor UnitNiosII
On-Chip Memory (RAM or ROM)OnChipMemory
IRQ MapperQsysInterconnect
IRQ Clock CrosserQsysInterconnect
JTAG UARTConfigurationProgramming
MM InterconnectQsysInterconnect
Avalon-ST Pipeline StageQsysInterconnect
Avalon-ST AdapterQsysInterconnect
Avalon-ST Error AdapterQsysInterconnect
Memory-Mapped DemultiplexerQsysInterconnect
Memory-Mapped MultiplexerQsysInterconnect
Avalon-MM Slave AgentQsysInterconnect
Avalon-ST Single Clock FIFOQsysInterconnect
Avalon-MM Slave TranslatorQsysInterconnect
Avalon-MM Master AgentQsysInterconnect
Avalon-MM Master TranslatorQsysInterconnect
Avalon-ST Handshake Clock CrosserQsysInterconnect
Memory-Mapped RouterQsysInterconnect
System ID PeripheralOther
Clocked Video Output II (4K Ready)AudioVideo
Video Input BridgeAudioVideo
Test Pattern Generator II (4K Ready)Other
Interval TimerPeripherals
Version1.0
FamilyArria 10
Device10AX115
Documentation
DocumentDescription
Document-
Development KitArria 10 GX FPGA Development Kit
Installation Package

Note: After downloading the design example, you must prepare the design template. The file you downloaded is of the form of a <project>.par file which contains a compressed version of your design files (similar to a .qar file) and metadata describing the project. The combination of this information is what constitutes a <project>.par file. In releases 16.0 or newer, you can simply double click on the <project>.par file and Quartus will launch that project.

The second means to bring up the project template is through the New Project Wizard (File -> New Project Wizard). After entering the project name and folder on the first panel, the second panel will ask you to specify an empty project or project template. Select project template. You will see a list of Design Templates projects that you have loaded prior as well as various "Baseline Pinout Designs" that contain the pinout and settings for a variety of development kits. If you don't see your design template in the list, click on the link that states install the Design Templates circled below:


Browse to the <project>.par file you downloaded, click next, followed by Finish, and your design template will be installed and displayed in the Project Navigator pane in Quartus.

Note: When a design is stored in the Design Store as a design template, it has been previously regression tested against the stated version of Quartus software. The regression ensures the design template passes analysis/synthesis/fitting/assembly steps in the Quartus design flow.

At the command-line, type the following command:

quartus_sh --platform_install –package <project directory>/top.par

Once the process completes, then type:

quartus_sh --platform –name top

Download   (The download link will expire on Jan. 21, 2021, 6:36 a.m., please refresh the page to get a new link.)
Quartus Prime VersionDownload Quartus Prime v17.0
Quartus Prime EditionStandard
VendorIntel


Last updated on Aug. 1, 2017, 10:18 a.m.