|Name||HDMI Tx-Only VIP Suite Design for Arria 10|
|Description||This reference design demonstrates the Intel FPGA High Definition Multimedia Interface (HDMI) 2.0 video connectivity IP core with a video processing pipeline based on IP cores from the Intel FPGA Video and Image Processing (VIP) Suite. This design is intended as a simple reference for interconnectivity between the HDMI IP core and the VIP Suite. This design demonstrates a simple configuration via a Nios II processor of a programmable oscillator on the Arria 10 GX FPGA Development Kit to drive the TX IOPLL and fPLL reference clocks.|
|Development Kit||Arria 10 GX FPGA Development Kit|
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Note: After downloading the design example, you must prepare the design template. The file you downloaded is of the form of a <project>.par file which contains a compressed version of your design files (similar to a .qar file) and metadata describing the project. The combination of this information is what constitutes a <project>.par file. In releases 16.0 or newer, you can simply double click on the <project>.par file and Quartus will launch that project.
Browse to the <project>.par file you downloaded, click next, followed by Finish, and your design template will be installed and displayed in the Project Navigator pane in Quartus.
Note: When a design is stored in the Design Store as a design template, it has been previously regression tested against the stated version of Quartus software. The regression ensures the design template passes analysis/synthesis/fitting/assembly steps in the Quartus design flow.
At the command-line, type the following command:
Once the process completes, then type:
|Quartus Prime Version||Download Quartus Prime v17.0|
|Quartus Prime Edition||Standard|
Last updated on Aug. 1, 2017, 10:18 a.m.