|Name||Dual Core Nios II Project with protected memory regions|
|Description||This tutorial describes a simple reference design for S/Labs' Interconnect IP for mapping a single memory region into private and shared memory regions for use with multiprocessor system without the requirement for an MMU or MPU.|
This reference design can be easily modified for other development boards and other Intel FPGA families.
Updated on 20 July 2018 to include Free Trial IP.
|Family||Cyclone 10 LP|
|Development Kit||Cyclone 10 LP FPGA Evaluation Kit|
Download (The download link will expire on Dec. 5, 2021, 9:48 a.m., please refresh the page to get a new link.)
Note: After downloading the design example, you must prepare the design template. The file you downloaded is of the form of a <project>.par file which contains a compressed version of your design files (similar to a .qar file) and metadata describing the project. The combination of this information is what constitutes a <project>.par file. In releases 16.0 or newer, you can simply double click on the <project>.par file and Quartus will launch that project.
Browse to the <project>.par file you downloaded, click next, followed by Finish, and your design template will be installed and displayed in the Project Navigator pane in Quartus.
Note: When a design is stored in the Design Store as a design template, it has been previously regression tested against the stated version of Quartus software. The regression ensures the design template passes analysis/synthesis/fitting/assembly steps in the Quartus design flow.
At the command-line, type the following command:
Once the process completes, then type:
|Quartus Prime Version||Download Quartus Prime v17.0|
|Quartus Prime Edition||Standard|
|Vendor||Synaptic Laboratories Ltd.|
Last updated on July 30, 2018, 8:45 a.m.