Design Store


Cyclone 10 LP Multiprocessor Nios II System Reference Design  


CategoryDesign Example
NameCyclone 10 LP Multiprocessor Nios II System Reference Design
DescriptionThis reference design demonstrates the features of the Intel® FPGA Nios® II processor and Qsys system integration tool that are useful for creating systems with multiple processors. This design using Qsys to build a multiprocessor system containing 4 processors. Each processor is in a subsystem, creating a hierarchy with four subsystems with a shared memory map, coordinated with pipeline bridges. This system demonstrates a solution for the classic Dining Philosophers’ Problem and shows case how to use the Nios II Software Build Tools (SBT) to create, build, download, and view stdio output in a console for four applications, using shell scripts.
Operating SystemNone
IP Core
IP CoreHeading
Nios II Gen2 ProcessorNiosII
Nios II Gen2 Processor UnitNiosII
IRQ MapperQsysInterconnect
JTAG UARTConfigurationProgramming
MM InterconnectQsysInterconnect
Avalon-ST AdapterQsysInterconnect
Avalon-ST Error AdapterQsysInterconnect
Memory-Mapped DemultiplexerQsysInterconnect
Memory-Mapped MultiplexerQsysInterconnect
Avalon-MM Master AgentQsysInterconnect
Avalon-MM Master TranslatorQsysInterconnect
Avalon-MM Slave AgentQsysInterconnect
Avalon-ST Single Clock FIFOQsysInterconnect
Avalon-MM Slave TranslatorQsysInterconnect
Memory-Mapped Traffic LimiterQsysInterconnect
Memory-Mapped RouterQsysInterconnect
On-Chip Memory (RAM or ROM)OnChipMemory
Altera Avalon MutexQsysInterconnect
Avalon-MM Pipeline BridgeQsysInterconnect
Reset ControllerQsysInterconnect
Interval TimerPeripherals
System ID PeripheralOther
Version1.0
FamilyCyclone 10 LP
Device10CL025
Documentation
DocumentDescription
Cyclone 10 LP Multiprocessor Nios II System Reference Design User Guide-
Development KitCyclone 10 LP FPGA Evaluation Kit
Installation Package

Note: After downloading the design example, you must prepare the design template. The file you downloaded is of the form of a <project>.par file which contains a compressed version of your design files (similar to a .qar file) and metadata describing the project. The combination of this information is what constitutes a <project>.par file. In releases 16.0 or newer, you can simply double click on the <project>.par file and Quartus will launch that project.

The second means to bring up the project template is through the New Project Wizard (File -> New Project Wizard). After entering the project name and folder on the first panel, the second panel will ask you to specify an empty project or project template. Select project template. You will see a list of Design Templates projects that you have loaded prior as well as various "Baseline Pinout Designs" that contain the pinout and settings for a variety of development kits. If you don't see your design template in the list, click on the link that states install the Design Templates circled below:


Browse to the <project>.par file you downloaded, click next, followed by Finish, and your design template will be installed and displayed in the Project Navigator pane in Quartus.

Note: When a design is stored in the Design Store as a design template, it has been previously regression tested against the stated version of Quartus software. The regression ensures the design template passes analysis/synthesis/fitting/assembly steps in the Quartus design flow.

At the command-line, type the following command:

quartus_sh --platform_install –package <project directory>/top.par

Once the process completes, then type:

quartus_sh --platform –name top

Download   (The download link will expire on Dec. 5, 2021, 9:57 a.m., please refresh the page to get a new link.)
Quartus Prime VersionDownload Quartus Prime v17.0
Quartus Prime EditionStandard
VendorIntel


Last updated on Aug. 27, 2017, 10:35 p.m.