|Name||Arria 10 two x8 Lanes JESD204B (Duplex) IP Cores Multi-Device Synchronization Reference Design using Nios II Processor|
|Description||This reference design demonstrates the implementation of two x8 Lanes JESD204B (Duplex) IP Cores synchronization in Arria 10 device through FMC loopback card. The main purpose is to emulate the interface between one converter card with two x8 Lanes JESD204B (Duplex) IP Cores.|
|Development Kit||Arria 10 GX FPGA Development Kit|
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Note: After downloading the design example, you must prepare the design template. The file you downloaded is of the form of a <project>.par file which contains a compressed version of your design files (similar to a .qar file) and metadata describing the project. The combination of this information is what constitutes a <project>.par file. In releases 16.0 or newer, you can simply double click on the <project>.par file and Quartus will launch that project.
Browse to the <project>.par file you downloaded, click next, followed by Finish, and your design template will be installed and displayed in the Project Navigator pane in Quartus.
Note: When a design is stored in the Design Store as a design template, it has been previously regression tested against the stated version of Quartus software. The regression ensures the design template passes analysis/synthesis/fitting/assembly steps in the Quartus design flow.
At the command-line, type the following command:
Once the process completes, then type:
|Quartus Prime Version||Download Quartus Prime v17.0|
|Quartus Prime Edition||Standard|
Last updated on June 22, 2018, 2:11 a.m.