Design Store


Accelerated Nios II/e Embedded System  


CategoryDesign Example
NameAccelerated Nios II/e Embedded System
DescriptionThis tutorial describes a simple reference design for S/Labs HBMC IP and S/Labs' system cache for accelerating the Nios II/e processor, targeted specifically to Intel Cyclone 10LP evaluation board. It also features Arduino style key components and pin headers, such as PIO, I2C and SPI interfaces. In addition, it supports a 16 Mbyte HyperRAM and 8 Mbyte EPCQ memories. The total embedded system fits in the smallest Cyclone 10 FPGA device.

This reference design can be easily modified for other development boards and other Intel FPGA families.


Updated on 20 July 2018 to include Free Trial IP.
Operating SystemNone
IP Core
IP CoreHeading
Version1.0
FamilyCyclone 10 LP
Device10CL025
Documentation
DocumentDescription
Nios II/e Tiny Embedded System OverviewOverview of the key benefits for using S/Labs System Cache and S/Labs Hyperbus memory controller
T006A: Arduino Style Nios II/e embedded systemThis tutorial describes a simple reference design for S/Labs HBMC IP and S/Labs' system cache for accelerating the Nios II/e processor, targeted specifically to Intel Cyclone 10LP evaluation board. It also features Arduino style key components and pin headers, such as PIO, I2C and SPI interfaces. In addition, it supports a 16 Mbyte HyperRAM and 8 Mbyte EPCQ memories. The total embedded system fits in the smallest Cyclone 10 FPGA device.
The License and Confidentiality AgreementBy downloading and using SLL's HBMC IP you are accepting and agreeing to the terms and conditions contained in this Agreement
Free Trial HBMC IPA Free Trial Bundle that contains S/Labs HBMC IP v3.1.1 for Intel FPGA. No registration required. Includes a Free License Credential issued to You for the Full Edition of the HBMC IP. This Credential: (a) includes a free License Key that You need to install into Quartus Prime; (b) has no expiration date; (c) permits 10 minutes of runtime; (d) permits the use of an unlimited number of concurrent developer seats; (e) works with any Network Interface Card (NIC) Identifier.
Request for S/Labs System Cache IP free trial licenseClick on the link to request a free trial license for S/Labs' System Cache IP.
Accelerated Nios II/e embedded system projectThis simple reference design demonstrates the use of S/Labs System Cache IP to improve the software performance of the Nios II/e when running from HyperRAM and/or EPCQ serial memory. It also includes connections to Arduino headers, I2C and SPI interfaces. Please download the Free Trial of the HBMC IP with 10 minute runtimes from the links above.
Synaptic Laboratories Limited website (URL)This is a URL link to Synaptic Laboratories Limited website.
Acclerated Nios II/e Embedded System on the MAX 10A similar reference design is also available for the MAX 10 FPGA (includes HyperFlash) at this link.
Development KitCyclone 10 LP FPGA Evaluation Kit
Installation Package

Note: After downloading the design example, you must prepare the design template. The file you downloaded is of the form of a <project>.par file which contains a compressed version of your design files (similar to a .qar file) and metadata describing the project. The combination of this information is what constitutes a <project>.par file. In releases 16.0 or newer, you can simply double click on the <project>.par file and Quartus will launch that project.

The second means to bring up the project template is through the New Project Wizard (File -> New Project Wizard). After entering the project name and folder on the first panel, the second panel will ask you to specify an empty project or project template. Select project template. You will see a list of Design Templates projects that you have loaded prior as well as various "Baseline Pinout Designs" that contain the pinout and settings for a variety of development kits. If you don't see your design template in the list, click on the link that states install the Design Templates circled below:


Browse to the <project>.par file you downloaded, click next, followed by Finish, and your design template will be installed and displayed in the Project Navigator pane in Quartus.

Note: When a design is stored in the Design Store as a design template, it has been previously regression tested against the stated version of Quartus software. The regression ensures the design template passes analysis/synthesis/fitting/assembly steps in the Quartus design flow.

At the command-line, type the following command:

quartus_sh --platform_install –package <project directory>/HyperNios_Arduino_Project_c10lp.par

Once the process completes, then type:

quartus_sh --platform –name HyperNios_Arduino_Project_c10lp

Download   (The download link will expire on Dec. 5, 2021, 10:53 a.m., please refresh the page to get a new link.)
Quartus Prime VersionDownload Quartus Prime v17.0
Quartus Prime EditionStandard
VendorSynaptic Laboratories Ltd.


Last updated on July 30, 2018, 8:42 a.m.