Design Store


Arria 10 two x8 Lanes JESD204B (Duplex) IP Cores Multi-Device Synchronization Reference Design using Nios II Processor  


CategoryDesign Example
NameArria 10 two x8 Lanes JESD204B (Duplex) IP Cores Multi-Device Synchronization Reference Design using Nios II Processor
DescriptionThis reference design demonstrates the implementation of two x8 Lanes JESD204B (Duplex) IP Cores synchronization in Arria 10 device through FMC loopback card. The main purpose is to emulate the interface between one converter card with two x8 Lanes JESD204B (Duplex) IP Cores.
Operating SystemNone
IP Core
IP CoreHeading
Version1.0
FamilyArria 10
Device10AX115
Documentation
DocumentDescription
AN814: Arria 10 two x8 Lanes JESD204B (Duplex) IP Cores Multi-Device Synchronization Reference Design using Nios II ProcessorApplication Note for arria 10 two x8 Lanes JESD204B (Duplex) IP Cores Multi-Device Synchronization Reference Design using Nios II Processor
Development KitArria 10 GX FPGA Development Kit
Installation Package

Note: After downloading the design example, you must prepare the design template. The file you downloaded is of the form of a <project>.par file which contains a compressed version of your design files (similar to a .qar file) and metadata describing the project. The combination of this information is what constitutes a <project>.par file. In releases 16.0 or newer, you can simply double click on the <project>.par file and Quartus will launch that project.

The second means to bring up the project template is through the New Project Wizard (File -> New Project Wizard). After entering the project name and folder on the first panel, the second panel will ask you to specify an empty project or project template. Select project template. You will see a list of Design Templates projects that you have loaded prior as well as various "Baseline Pinout Designs" that contain the pinout and settings for a variety of development kits. If you don't see your design template in the list, click on the link that states install the Design Templates circled below:


Browse to the <project>.par file you downloaded, click next, followed by Finish, and your design template will be installed and displayed in the Project Navigator pane in Quartus.

Note: When a design is stored in the Design Store as a design template, it has been previously regression tested against the stated version of Quartus software. The regression ensures the design template passes analysis/synthesis/fitting/assembly steps in the Quartus design flow.

At the command-line, type the following command:

quartus_sh --platform_install –package <project directory>/A10_jesd204b_2x8L_nios_ref_design_17_0pro.par

Once the process completes, then type:

quartus_sh --platform –name A10_jesd204b_2x8L_nios_ref_design_17_0pro

Download   (The download link will expire on Feb. 28, 2021, 2:49 p.m., please refresh the page to get a new link.)
Quartus Prime VersionDownload Quartus Prime v17.0
Quartus Prime EditionPro
VendorIntel


Last updated on June 22, 2018, 2:11 a.m.