Design Store


Video and Image Processing Design Example on DVI Display  


CategoryDesign Example
NameVideo and Image Processing Design Example on DVI Display
DescriptionThe Altera Video and Image Processing Design Example demonstrates the following items:
(1) A framework for rapid development of video and image processing systems.
(2) Dynamic scaling, clipping, flashing, moving, sharpening and FIR filtering of both standard definition (SD) and high definition (HD) inputs.
(3) Picture-in-picture mixing with a background layer.
(4) Run-time control of different parts of the system, including a radar that uses on-screen display functions.
(5) Debugging components for monitoring the video stream from within the data path.
The design example runs from the Bitec HSMC DVI and Bitec HSMC Quad Video daughter cards. The standard definition video stream is in either National Television System Committee (NTSC) or phase alternation line (PAL) format. The high-definition video stream uses a digital video interface (DVI) port.
Operating SystemNone
IP Core
IP CoreHeading
Avalon-ST Video MonitorQsysInterconnect
Avalon-ST Video Monitor CoreQsysInterconnect
Avalon-ST MultiplexerQsysInterconnect
Avalon-MM Pipeline BridgeQsysInterconnect
MM InterconnectQsysInterconnect
Avalon-ST AdapterQsysInterconnect
Avalon-ST Error AdapterQsysInterconnect
Memory-Mapped DemultiplexerQsysInterconnect
Memory-Mapped MultiplexerQsysInterconnect
Avalon-MM Master AgentQsysInterconnect
Memory-Mapped Traffic LimiterQsysInterconnect
Avalon-MM Master TranslatorQsysInterconnect
Avalon-MM Slave AgentQsysInterconnect
Avalon-ST Single Clock FIFOQsysInterconnect
Avalon-MM Slave TranslatorQsysInterconnect
Memory-Mapped RouterQsysInterconnect
avalon streaming monitorQsysInterconnect
Avalon-ST Pipeline StageQsysInterconnect
video pixel sampling monitorAudioVideo
Avalon-MM Clock Crossing BridgeQsysInterconnect
Scaler IIAudioVideo
Scaler Algorithmic CoreAudioVideo
Clipper II (4K Ready)AudioVideo
Clocked Video Input II (4K Ready)AudioVideo
Frame Buffer II (4K Ready)AudioVideo
Video Input BridgeAudioVideo
IRQ MapperQsysInterconnect
JTAG UARTConfigurationProgramming
DDR3 SDRAM Controller with UniPHYExternalMemoryInterfaces
Altera DDR3 Nextgen Memory ControllerExternalMemoryInterfaces
Altera Nextgen Memory Controller MM-ST AdapterExternalMemoryInterfaces
Altera DDR3 Nextgen Memory Controller CoreExternalMemoryInterfaces
External Memory DLL blockExternalMemoryInterfaces
altera_jtag_avalon_masterQsysInterconnect
Avalon-ST Bytes to Packets ConverterQsysInterconnect
Avalon-ST Channel AdapterQsysInterconnect
Avalon-ST JTAG InterfaceQsysInterconnect
Avalon-ST Packets to Bytes ConverterQsysInterconnect
Reset ControllerQsysInterconnect
Avalon-ST Timing AdapterQsysInterconnect
Avalon Packets to Transaction ConverterQsysInterconnect
Altera DDR3 AFI MultiplexerExternalMemoryInterfaces
External Memory OCT blockExternalMemoryInterfaces
DDR3 SDRAM External Memory PHYExternalMemoryInterfaces
DDR3 SDRAM External Memory PLL/DLL/OCT blockExternalMemoryInterfaces
DDR3 SDRAM Qsys SequencerExternalMemoryInterfaces
Memory-Mapped Width AdapterQsysInterconnect
Avalon-ST Handshake Clock CrosserQsysInterconnect
Memory-Mapped Burst AdapterQsysInterconnect
Color Space Converter (CSC) II (4K Ready)AudioVideo
Deinterlacer II (with Sobel based HQ mode)AudioVideo
Clocked Video Output II (4K Ready)AudioVideo
On-Chip Memory (RAM or ROM)OnChipMemory
Frame ReaderOther
Interval TimerPeripherals
Trace SystemQsysInterconnect
Avalon ST Debug FabricQsysInterconnect
Avalon-ST DemultiplexerQsysInterconnect
Altera Management Reset BlockOther
JTAG Debug LinkConfigurationProgramming
JTAG Debug Link (internal module)ConfigurationProgramming
Trace FabricQsysInterconnect
altera_trace_capture_controllerQsysInterconnect
Avalon-ST Data Format AdapterQsysInterconnect
Trace ROMQsysInterconnect
Timestamp monitorQsysInterconnect
transacto_liteSimulationDebugVerification
Vectored Interrupt ControllerQsysInterconnect
VIC CSR BlockAudioVideo
VIC Priority BlockAudioVideo
VIC Vector BlockAudioVideo
Altera PLLClocksPLLsResets
Nios II Gen2 ProcessorNiosII
Mixer II (4K Ready)AudioVideo
2D-FIRDSP
FIR Algorithmic CoreDSP
Version1.0
FamilyCyclone V
Device5CGTFD9
Documentation
DocumentDescription
Video and Image Processing Design ExampleDocument describing theory of operation, what results to expect when running this design on the development kit and how to reconstruct the design.
Development KitCyclone V GT FPGA Development Kit
Installation Package

Note: After downloading the design example, you must prepare the design template. The file you downloaded is of the form of a <project>.par file which contains a compressed version of your design files (similar to a .qar file) and metadata describing the project. The combination of this information is what constitutes a <project>.par file. In releases 16.0 or newer, you can simply double click on the <project>.par file and Quartus will launch that project.

The second means to bring up the project template is through the New Project Wizard (File -> New Project Wizard). After entering the project name and folder on the first panel, the second panel will ask you to specify an empty project or project template. Select project template. You will see a list of Design Templates projects that you have loaded prior as well as various "Baseline Pinout Designs" that contain the pinout and settings for a variety of development kits. If you don't see your design template in the list, click on the link that states install the Design Templates circled below:


Browse to the <project>.par file you downloaded, click next, followed by Finish, and your design template will be installed and displayed in the Project Navigator pane in Quartus.

Note: When a design is stored in the Design Store as a design template, it has been previously regression tested against the stated version of Quartus software. The regression ensures the design template passes analysis/synthesis/fitting/assembly steps in the Quartus design flow.

At the command-line, type the following command:

quartus_sh --platform_install –package <project directory>/CVGT_VIP_EXAMPLE.par

Once the process completes, then type:

quartus_sh --platform –name CVGT_VIP_EXAMPLE

Download   (The download link will expire on June 23, 2021, 8:36 a.m., please refresh the page to get a new link.)
Quartus Prime VersionDownload Quartus Prime v16.1
Quartus Prime EditionStandard
VendorIntel


Last updated on Feb. 9, 2018, 3:26 a.m.