Design Store


UART RS-232 Maximum Baud Rate Reference Design   


CategoryDesign Example
NameUART RS-232 Maximum Baud Rate Reference Design
DescriptionThis example is a test functionality for UART RS-232 Serial Port IP which contains a NIOS® II processor and Dual UART RS-232 IP. The design example implements a basic UART RS-232 functionality of Variable Baud Rate On real-time basis. This means the developer can set the required Baud Rate of data transfer from NIOS II Application. Furthermore, this design demonstrates a standard method of developing a UART Application with NIOS II.
Operating SystemBareMetal
IP Core
IP CoreHeading
IRQ MapperQsysInterconnect
JTAG UARTConfigurationProgramming
PIO (Parallel I/O)Other
MM InterconnectQsysInterconnect
Avalon-ST AdapterQsysInterconnect
Avalon-ST Error AdapterQsysInterconnect
Memory-Mapped DemultiplexerQsysInterconnect
Memory-Mapped MultiplexerQsysInterconnect
Avalon-MM Slave AgentQsysInterconnect
Avalon-ST Single Clock FIFOQsysInterconnect
Avalon-MM Slave TranslatorQsysInterconnect
Avalon-MM Master AgentQsysInterconnect
Avalon-MM Master TranslatorQsysInterconnect
Memory-Mapped RouterQsysInterconnect
Nios II Gen2 ProcessorNiosII
Nios II Gen2 Processor UnitNiosII
On-Chip Memory (RAM or ROM)OnChipMemory
Reset ControllerQsysInterconnect
UART (RS-232 Serial Port)Other
Version1.0
FamilyCyclone V
Device5CEBA4
Documentation
DocumentDescription
Design Example User GuideThis is the user guide of the design example to show step-by-step how to run the design on the FPGA board.
Development KitDE0-CV Development Board
Installation Package

Note: After downloading the design example, you must prepare the design template. The file you downloaded is of the form of a <project>.par file which contains a compressed version of your design files (similar to a .qar file) and metadata describing the project. The combination of this information is what constitutes a <project>.par file. In releases 16.0 or newer, you can simply double click on the <project>.par file and Quartus will launch that project.

The second means to bring up the project template is through the New Project Wizard (File -> New Project Wizard). After entering the project name and folder on the first panel, the second panel will ask you to specify an empty project or project template. Select project template. You will see a list of Design Templates projects that you have loaded prior as well as various "Baseline Pinout Designs" that contain the pinout and settings for a variety of development kits. If you don't see your design template in the list, click on the link that states install the Design Templates circled below:


Browse to the <project>.par file you downloaded, click next, followed by Finish, and your design template will be installed and displayed in the Project Navigator pane in Quartus.

Note: When a design is stored in the Design Store as a design template, it has been previously regression tested against the stated version of Quartus software. The regression ensures the design template passes analysis/synthesis/fitting/assembly steps in the Quartus design flow.

At the command-line, type the following command:

quartus_sh --platform_install –package <project directory>/CV_SOC_UART.par

Once the process completes, then type:

quartus_sh --platform –name CV_SOC_UART

Download   (The download link will expire on Jan. 26, 2022, 12:38 p.m., please refresh the page to get a new link.)
Quartus Prime VersionDownload Quartus Prime v16.1
Quartus Prime EditionStandard
VendorIntel


Image 1


Last updated on June 22, 2018, 2:11 a.m.