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Nios II + Qsys "Hello World" Lab - MAX10 DE10 Lite  

NameNios II + Qsys "Hello World" Lab - MAX10 DE10 Lite
DescriptionThis step by step lab shows a user how to build a Nios II Qsys based system that includes GPIO, UART and on-chip memory. This lab requires the MAX 10 DE10-Lite Development Kit from Terasic. The appendix B in the lab manual describes how to combine the SW image with the HW .sof file.
Operating SystemNone
IP Core
IP CoreHeading
IRQ MapperQsysInterconnect
PIO (Parallel I/O)Other
MM InterconnectQsysInterconnect
Avalon-ST AdapterQsysInterconnect
Avalon-ST Error AdapterQsysInterconnect
Memory-Mapped DemultiplexerQsysInterconnect
Memory-Mapped MultiplexerQsysInterconnect
Avalon-MM Slave AgentQsysInterconnect
Avalon-ST Single Clock FIFOQsysInterconnect
Avalon-MM Slave TranslatorQsysInterconnect
Avalon-MM Master AgentQsysInterconnect
Avalon-MM Master TranslatorQsysInterconnect
Memory-Mapped RouterQsysInterconnect
Nios II Gen2 ProcessorNiosII
Nios II Gen2 Processor UnitNiosII
On-Chip Memory (RAM or ROM)OnChipMemory
Reset ControllerQsysInterconnect
JTAG UARTConfigurationProgramming
FamilyMAX 10
Hello_world_lab_DE10-LiteWhole description to perform the hello world lab with Nios 2 on DE10-Lite Development kit
Development KitMAX 10 DE10 - Lite
Quartus Prime VersionDownload Quartus Prime v16.1
Quartus Prime EditionStandard

Last updated on Feb. 7, 2018, 8:17 a.m.