Design Store


MAX10 Remote System Upgrade (RSU) over UART for Nios II Processor  


CategoryDesign Example
NameMAX10 Remote System Upgrade (RSU) over UART for Nios II Processor
DescriptionThe reference design provides a simple application that implements basic remote configuration features in Nios II-based systems for MAX 10 FPGA devices. The UART interface included in the MAX 10 FPGA Development Kit is used together with Altera UART IP core to provide the remote configuration functionality.
Operating SystemNone
IP Core
IP CoreHeading
Avalon ALTPLLClocksPLLsResets
Altera Dual BootConfigurationProgramming
Altera Generic QUAD SPI controllerConfigurationProgramming
Altera ASMI ParallelConfigurationProgramming
Altera EPCQ Serial Flash controller coreConfigurationProgramming
Altera SOFT ASMIBLOCKOther
IRQ MapperQsysInterconnect
IRQ Clock CrosserQsysInterconnect
MM InterconnectQsysInterconnect
Avalon-ST AdapterQsysInterconnect
Avalon-ST Error AdapterQsysInterconnect
Memory-Mapped DemultiplexerQsysInterconnect
Memory-Mapped MultiplexerQsysInterconnect
Avalon-ST Handshake Clock CrosserQsysInterconnect
Avalon-MM Slave AgentQsysInterconnect
Avalon-ST Single Clock FIFOQsysInterconnect
Avalon-MM Slave TranslatorQsysInterconnect
Memory-Mapped Burst AdapterQsysInterconnect
Avalon-MM Master AgentQsysInterconnect
Memory-Mapped Traffic LimiterQsysInterconnect
Avalon-MM Master TranslatorQsysInterconnect
Memory-Mapped RouterQsysInterconnect
Nios II Gen2 ProcessorNiosII
Altera On-Chip FlashFlash
On-Chip Memory (RAM or ROM)OnChipMemory
Reset ControllerQsysInterconnect
System ID PeripheralOther
UART (RS-232 Serial Port)Other
Version1.0
FamilyMAX 10
Device10M50DA
Documentation
DocumentDescription
Remote System Upgrade over UART with the Nios II Processor for MAX 10 DevicesThis is the application note for the reference design.
Development KitMAX 10 FPGA Development Kit
Installation Package

Note: After downloading the design example, you must prepare the design template. The file you downloaded is of the form of a <project>.par file which contains a compressed version of your design files (similar to a .qar file) and metadata describing the project. The combination of this information is what constitutes a <project>.par file. In releases 16.0 or newer, you can simply double click on the <project>.par file and Quartus will launch that project.

The second means to bring up the project template is through the New Project Wizard (File -> New Project Wizard). After entering the project name and folder on the first panel, the second panel will ask you to specify an empty project or project template. Select project template. You will see a list of Design Templates projects that you have loaded prior as well as various "Baseline Pinout Designs" that contain the pinout and settings for a variety of development kits. If you don't see your design template in the list, click on the link that states install the Design Templates circled below:


Browse to the <project>.par file you downloaded, click next, followed by Finish, and your design template will be installed and displayed in the Project Navigator pane in Quartus.

Note: When a design is stored in the Design Store as a design template, it has been previously regression tested against the stated version of Quartus software. The regression ensures the design template passes analysis/synthesis/fitting/assembly steps in the Quartus design flow.

At the command-line, type the following command:

quartus_sh --platform_install –package <project directory>/max10_RSU.par

Once the process completes, then type:

quartus_sh --platform –name max10_RSU

Download
Total Downloads443 (From 02 Feb 2017 to 06 Dec 2019)
Quartus Prime VersionDownload Quartus Prime v16.1
Quartus Prime EditionStandard
VendorIntel


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Last updated on Feb. 21, 2017, 10:33 p.m.