Design Store


DisplayPort UHD Scaler and Mixer Design Example  


CategoryDesign Example
NameDisplayPort UHD Scaler and Mixer Design Example
Description The design runs on Arria 10 GX FPGA Development Kit. The Bitec FMC daughter card is used to receive video data from the Graphic Processor Unit (GPU) on the PC graphic card and transmit video data to a monitor. This reference design receives video data (either 1080p or 2160p resolution) over the DP RX link. The received video is converted to the Avalon-ST video stream, up or down scaling the video stream and stored into the external memory. The buffered image is then mixed with a 3840 x 2160 color bar background and OSD icon and is sent to the DP source. The combined image is transmitted to a DP capable monitor over DP TX link.
Operating SystemNone
IP Core
IP CoreHeading
Avalon FIFO MemoryOnChipMemory
Nios II Gen2 ProcessorNiosII
Nios II Gen2 Processor UnitNiosII
DisplayPortAudioVideo
IRQ MapperQsysInterconnect
IRQ Clock CrosserQsysInterconnect
JTAG UARTConfigurationProgramming
altera_jtag_avalon_masterQsysInterconnect
Avalon-ST Bytes to Packets ConverterQsysInterconnect
Avalon-ST Channel AdapterQsysInterconnect
Avalon-ST Single Clock FIFOQsysInterconnect
Avalon-ST JTAG InterfaceQsysInterconnect
Avalon-ST Packets to Bytes ConverterQsysInterconnect
Reset ControllerQsysInterconnect
Avalon-ST Timing AdapterQsysInterconnect
Avalon Packets to Transaction ConverterQsysInterconnect
MM InterconnectQsysInterconnect
Avalon-MM Slave AgentQsysInterconnect
Avalon-MM Slave TranslatorQsysInterconnect
Avalon-ST AdapterQsysInterconnect
Avalon-ST Error AdapterQsysInterconnect
Memory-Mapped DemultiplexerQsysInterconnect
Memory-Mapped MultiplexerQsysInterconnect
Avalon-MM Master AgentQsysInterconnect
Avalon-MM Master TranslatorQsysInterconnect
Avalon-ST Handshake Clock CrosserQsysInterconnect
Memory-Mapped Traffic LimiterQsysInterconnect
Memory-Mapped RouterQsysInterconnect
PIO (Parallel I/O)Other
On-Chip Memory (RAM or ROM)OnChipMemory
Interval TimerPeripherals
System ID PeripheralOther
Avalon-ST Data Format AdapterQsysInterconnect
Avalon-ST Video stream cleanerQsysInterconnect
Video Input BridgeAudioVideo
Clipper II (4K Ready)AudioVideo
Clocked Video Input II (4K Ready)AudioVideo
Clocked Video Output II (4K Ready)AudioVideo
Arria 10 External Memory InterfacesExternalMemoryInterfaces
EMIF Core Component for 20nm FamiliesExternalMemoryInterfaces
Avalon-MM Pipeline BridgeQsysInterconnect
Mixer II (4K Ready)AudioVideo
Scaler IIAudioVideo
Scaler Algorithmic CoreAudioVideo
Frame Buffer II (4K Ready)AudioVideo
Arria 10 Transceiver Native PHYTransceiverPHY
Transceiver PHY Reset ControllerTransceiverPHY
Arria 10 FPLLClocksPLLsResets
Altera GPIOOther
Altera GPIO CoreOther
Altera IOPLLClocksPLLsResets
Altera Arria 10 XCVR Reset SequencerOther
Version1.0
FamilyArria 10
Device10AX115
Documentation
DocumentDescription
Arria 10 UHD Scaler and Mixer Design Example User Guide This document describes a reference design that demonstrates Altera DisplayPort (DP) video connectivity IP core with a video processing pipeline based on IP cores from the Altera Video and Image Processing suite. The design delivers high quality up, down scaling and video mixing. The reference design targets Arria 10 devices and use the latest 4K ready IP cores from the Video and Image Processing Suite.
Development KitArria 10 GX FPGA Development Kit
Installation Package

Note: After downloading the design example, you must prepare the design template. The file you downloaded is of the form of a <project>.par file which contains a compressed version of your design files (similar to a .qar file) and metadata describing the project. The combination of this information is what constitutes a <project>.par file. In releases 16.0 or newer, you can simply double click on the <project>.par file and Quartus will launch that project.

The second means to bring up the project template is through the New Project Wizard (File -> New Project Wizard). After entering the project name and folder on the first panel, the second panel will ask you to specify an empty project or project template. Select project template. You will see a list of Design Templates projects that you have loaded prior as well as various "Baseline Pinout Designs" that contain the pinout and settings for a variety of development kits. If you don't see your design template in the list, click on the link that states install the Design Templates circled below:


Browse to the <project>.par file you downloaded, click next, followed by Finish, and your design template will be installed and displayed in the Project Navigator pane in Quartus.

Note: When a design is stored in the Design Store as a design template, it has been previously regression tested against the stated version of Quartus software. The regression ensures the design template passes analysis/synthesis/fitting/assembly steps in the Quartus design flow.

At the command-line, type the following command:

quartus_sh --platform_install –package <project directory>/UHD_Scaler_and_Mixer.par

Once the process completes, then type:

quartus_sh --platform –name UHD_Scaler_and_Mixer

Download   (The download link will expire on May 11, 2021, 4:35 a.m., please refresh the page to get a new link.)
Quartus Prime VersionDownload Quartus Prime v16.1
Quartus Prime EditionStandard
VendorIntel


Last updated on Dec. 13, 2017, 11:27 a.m.