Design Store

Board Update Portal utilizing EPCQ Flash Memory Reference Design  

CategoryDesign Example
NameBoard Update Portal utilizing EPCQ Flash Memory Reference Design
DescriptionThis example is a web-based board update portal (BUP) which contains a NIOS® II processor and a Triple Speed Ethernet media access control (MAC) MegaCore® function. The design example implements a basic remote configuration features in Nios II-based systems utilizing EPCQ flash memory for Arria 10 GX FPGA device. The design can obtain an IP address from any DHCP server and serve a web page from the flash on the board to any host computer on the same network. Furthermore, this design supports a static IP address, where the developer must insert the required design manually before loading the design into EPCQ flash. The web page allows you to upload new design images for both user hardware and user software. Furthermore, you can trigger reconfiguration from factory image to user image through the web page.
Operating SystemBareMetal
IP Core
IP CoreHeading
Avalon-ST AdapterQsysInterconnect
Avalon-ST Timing AdapterQsysInterconnect
PIO (Parallel I/O)Other
Nios II Gen2 ProcessorNiosII
Nios II Gen2 Processor UnitNiosII
On-Chip Memory (RAM or ROM)OnChipMemory
Altera Serial Flash ControllerFlash
Altera ASMI ParallelConfigurationProgramming
Altera EPCQ Serial Flash controller coreConfigurationProgramming
Interval TimerPeripherals
Altera IOPLLClocksPLLsResets
IRQ MapperQsysInterconnect
IRQ Clock CrosserQsysInterconnect
JTAG UARTConfigurationProgramming
MM InterconnectQsysInterconnect
Avalon-ST Error AdapterQsysInterconnect
Memory-Mapped DemultiplexerQsysInterconnect
Memory-Mapped MultiplexerQsysInterconnect
Avalon-MM Master AgentQsysInterconnect
Avalon-MM Master TranslatorQsysInterconnect
Avalon-MM Slave AgentQsysInterconnect
Avalon-ST Single Clock FIFOQsysInterconnect
Avalon-MM Slave TranslatorQsysInterconnect
Avalon-ST Handshake Clock CrosserQsysInterconnect
Memory-Mapped Burst AdapterQsysInterconnect
Memory-Mapped RouterQsysInterconnect
Memory-Mapped Traffic LimiterQsysInterconnect
Avalon-MM Pipeline BridgeQsysInterconnect
Reset ControllerQsysInterconnect
Altera Remote UpdateConfigurationProgramming
Altera Remote Update CoreConfigurationProgramming
Scatter-Gather DMA ControllerBridgesAndAdaptors
System ID PeripheralOther
Triple-Speed EthernetEthernet
Altera LVDS SERDESOther
altera_lvds_core20Other
Version1.0
FamilyArria 10
Device10AX115
Documentation
DocumentDescription
Reference Design User GuideThis User Guide will show you the step-by-step of how to run the design correctly.
Development KitArria 10 GX FPGA Development Kit
Installation Package

Note: After downloading the design example, you must prepare the design template. The file you downloaded is of the form of a <project>.par file which contains a compressed version of your design files (similar to a .qar file) and metadata describing the project. The combination of this information is what constitutes a <project>.par file. In releases 16.0 or newer, you can simply double click on the <project>.par file and Quartus will launch that project.

The second means to bring up the project template is through the New Project Wizard (File -> New Project Wizard). After entering the project name and folder on the first panel, the second panel will ask you to specify an empty project or project template. Select project template. You will see a list of Design Templates projects that you have loaded prior as well as various "Baseline Pinout Designs" that contain the pinout and settings for a variety of development kits. If you don't see your design template in the list, click on the link that states install the Design Templates circled below:


Browse to the <project>.par file you downloaded, click next, followed by Finish, and your design template will be installed and displayed in the Project Navigator pane in Quartus.

Note: When a design is stored in the Design Store as a design template, it has been previously regression tested against the stated version of Quartus software. The regression ensures the design template passes analysis/synthesis/fitting/assembly steps in the Quartus design flow.

At the command-line, type the following command:

quartus_sh --platform_install –package <project directory>/A10_GX_BUP_Design.par

Once the process completes, then type:

quartus_sh --platform –name A10_GX_BUP_Design

Download
Total Downloads71 (From 23 Dec 2016 to 22 Oct 2019)
Quartus Prime VersionDownload Quartus Prime v16.1
Quartus Prime EditionStandard
VendorIntel


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Last updated on June 22, 2018, 2:11 a.m.