Design Store

Arria 10 Triple-Speed Ethernet with IEEE 1588v2 and Native PHY design example  

CategoryDesign Example
NameArria 10 Triple-Speed Ethernet with IEEE 1588v2 and Native PHY design example
DescriptionThis design example demonstrates the functionalities of the Intel® Arria 10 Triple-Speed Ethernet (TSE) with IEEE 1588v2 feature and Intel® Arria 10 Transceiver Native PHY IP cores on Intel® Arria 10 SI development board.
Operating SystemNone
IP Core
IP Core (26)
IP CoreHeading
altera_jtag_avalon_masterQsysInterconnect
Avalon-ST Bytes to Packets ConverterQsysInterconnect
Avalon-ST Channel AdapterQsysInterconnect
Avalon-ST Single Clock FIFOQsysInterconnect
Avalon-ST JTAG InterfaceQsysInterconnect
Avalon-ST Packets to Bytes ConverterQsysInterconnect
Reset ControllerQsysInterconnect
Avalon-ST Timing AdapterQsysInterconnect
Avalon Packets to Transaction ConverterQsysInterconnect
Avalon-MM Slave TranslatorQsysInterconnect
Avalon-MM Master TranslatorQsysInterconnect
Avalon-MM Clock Crossing BridgeQsysInterconnect
MM InterconnectQsysInterconnect
Avalon-ST AdapterQsysInterconnect
Avalon-ST Error AdapterQsysInterconnect
Memory-Mapped DemultiplexerQsysInterconnect
Memory-Mapped MultiplexerQsysInterconnect
Avalon-MM Slave AgentQsysInterconnect
Avalon-MM Master AgentQsysInterconnect
Memory-Mapped RouterQsysInterconnect
Memory-Mapped Traffic LimiterQsysInterconnect
Ethernet IEEE 1588 TOD SynchonizerEthernet
Arria 10 Transceiver Native PHYTransceiverPHY
Transceiver PHY Reset ControllerTransceiverPHY
Arria 10 FPLLClocksPLLsResets
Altera Arria 10 XCVR Reset SequencerOther
Version1.0
FamilyArria 10
Device10AX115
Documentation
DocumentDescription
Arria 10 Triple Speed Ethernet and Native PHY with IEEE 1588v2 Design Example User Guide-
Development KitArria 10 GX Transceiver Signal Integrity Development Kit
Installation Package
Prepare the design template in the Quartus Prime software GUI (version 14.1 and later)

Note: After downloading the design example, you must prepare the design template. The file you downloaded is of the form of a <project>.par file which contains a compressed version of your design files (similar to a .qar file) and metadata describing the project. The combination of this information is what constitutes a <project>.par file. In releases 16.0 or newer, you can simply double click on the <project>.par file and Quartus will launch that project.

The second means to bring up the project template is through the New Project Wizard (File -> New Project Wizard). After entering the project name and folder on the first panel, the second panel will ask you to specify an empty project or project template. Select project template. You will see a list of Design Templates projects that you have loaded prior as well as various "Baseline Pinout Designs" that contain the pinout and settings for a variety of development kits. If you don't see your design template in the list, click on the link that states install the Design Templates circled below:


Browse to the <project>.par file you downloaded, click next, followed by Finish, and your design template will be installed and displayed in the Project Navigator pane in Quartus.

Note: When a design is stored in the Design Store as a design template, it has been previously regression tested against the stated version of Quartus software. The regression ensures the design template passes analysis/synthesis/fitting/assembly steps in the Quartus design flow.

Prepare the design template in the Quartus Prime software command-line

At the command-line, type the following command:

quartus_sh --platform_install –package <project directory>/altera_eth_tse_native_phy_w_1588.par

Once the process completes, then type:

quartus_sh --platform –name altera_eth_tse_native_phy_w_1588

Download
Total Downloads69 (From 06 Jun 2017 to 12 Oct 2019)
Quartus Prime VersionDownload Quartus Prime v16.1
Quartus Prime EditionStandard
VendorIntel

Last updated on June 20, 2017, 11:31 a.m.