|Name||Arria 10 Low Latency Ethernet 10G MAC and XAUI PHY Reference Design|
|Description||This design example describes the Arria 10® Low Latency Ethernet 10G MAC and XAUI PHY design that demonstrate Ethernet operations of the Altera® Arria 10® Low Latency Ethernet 10G MAC and XAUI PHY IP with Dual XAUI to SFP+ HSMC board targeted on Altera Arria 10® FPGA development kit. It provides flexible test and demonstration platforms on which user can control, test, and monitor the Ethernet operations using system loopback at various points.|
|Development Kit||Arria 10 GX FPGA Development Kit|
Note: After downloading the design example, you must prepare the design template. The file you downloaded is of the form of a <project>.par file which contains a compressed version of your design files (similar to a .qar file) and metadata describing the project. The combination of this information is what constitutes a <project>.par file. In releases 16.0 or newer, you can simply double click on the <project>.par file and Quartus will launch that project.
Browse to the <project>.par file you downloaded, click next, followed by Finish, and your design template will be installed and displayed in the Project Navigator pane in Quartus.
Note: When a design is stored in the Design Store as a design template, it has been previously regression tested against the stated version of Quartus software. The regression ensures the design template passes analysis/synthesis/fitting/assembly steps in the Quartus design flow.
At the command-line, type the following command:
Once the process completes, then type:
|Total Downloads||131 (From 27 Jan 2017 to 20 Sep 2018)|
|Quartus Prime Version||Download Quartus Prime v16.1|
|Quartus Prime Edition||Standard|
Last updated on April 26, 2017, 10:43 a.m.