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Arria 10 Low Latency Ethernet 10G MAC and XAUI PHY Reference Design   

CategoryDesign Example
NameArria 10 Low Latency Ethernet 10G MAC and XAUI PHY Reference Design
DescriptionThis design example describes the Arria 10® Low Latency Ethernet 10G MAC and XAUI PHY design that demonstrate Ethernet operations of the Altera® Arria 10® Low Latency Ethernet 10G MAC and XAUI PHY IP with Dual XAUI to SFP+ HSMC board targeted on Altera Arria 10® FPGA development kit. It provides flexible test and demonstration platforms on which user can control, test, and monitor the Ethernet operations using system loopback at various points.
Operating SystemNone
IP Core
IP CoreHeading
Altera Arria 10 XCVR Reset SequencerOther
Avalon-MM Slave TranslatorQsysInterconnect
altera_jtag_avalon_masterQsysInterconnect
Avalon-ST Bytes to Packets ConverterQsysInterconnect
Avalon-ST Channel AdapterQsysInterconnect
Avalon-ST Single Clock FIFOQsysInterconnect
Avalon-ST JTAG InterfaceQsysInterconnect
Avalon-ST Packets to Bytes ConverterQsysInterconnect
Reset ControllerQsysInterconnect
Avalon-ST Timing AdapterQsysInterconnect
Avalon Packets to Transaction ConverterQsysInterconnect
Avalon-MM Master TranslatorQsysInterconnect
MM InterconnectQsysInterconnect
Avalon-ST AdapterQsysInterconnect
Avalon-ST Error AdapterQsysInterconnect
Memory-Mapped DemultiplexerQsysInterconnect
Memory-Mapped MultiplexerQsysInterconnect
Avalon-ST Handshake Clock CrosserQsysInterconnect
Avalon-MM Slave AgentQsysInterconnect
Memory-Mapped Burst AdapterQsysInterconnect
Avalon-MM Master AgentQsysInterconnect
Memory-Mapped Traffic LimiterQsysInterconnect
Memory-Mapped RouterQsysInterconnect
Arria 10 Transceiver ATX PLLTransceiverPLL
Arria 10 FPLLClocksPLLsResets
Low Latency Ethernet 10G MACEthernet
XAUI PHYEthernet
Arria 10 Transceiver Native PHYTransceiverPHY
Ethernet MDIOEthernet
Version16.1
FamilyArria 10
Device10AX115
Documentation
DocumentDescription
User Guide-
Development KitArria 10 GX FPGA Development Kit
Installation Package

Note: After downloading the design example, you must prepare the design template. The file you downloaded is of the form of a <project>.par file which contains a compressed version of your design files (similar to a .qar file) and metadata describing the project. The combination of this information is what constitutes a <project>.par file. In releases 16.0 or newer, you can simply double click on the <project>.par file and Quartus will launch that project.

The second means to bring up the project template is through the New Project Wizard (File -> New Project Wizard). After entering the project name and folder on the first panel, the second panel will ask you to specify an empty project or project template. Select project template. You will see a list of Design Templates projects that you have loaded prior as well as various "Baseline Pinout Designs" that contain the pinout and settings for a variety of development kits. If you don't see your design template in the list, click on the link that states install the Design Templates circled below:


Browse to the <project>.par file you downloaded, click next, followed by Finish, and your design template will be installed and displayed in the Project Navigator pane in Quartus.

Note: When a design is stored in the Design Store as a design template, it has been previously regression tested against the stated version of Quartus software. The regression ensures the design template passes analysis/synthesis/fitting/assembly steps in the Quartus design flow.

At the command-line, type the following command:

quartus_sh --platform_install –package <project directory>/a10_ll10gmac_xauiphy.par

Once the process completes, then type:

quartus_sh --platform –name a10_ll10gmac_xauiphy

Download
Total Downloads131 (From 27 Jan 2017 to 20 Sep 2018)
Quartus Prime VersionDownload Quartus Prime v16.1
Quartus Prime EditionStandard
VendorIntel


Last updated on April 26, 2017, 10:43 a.m.