|Name||Arria 10 Scalable 10G Ethernet MAC+Native PHY with IEEE1588v2 Design|
|Description||This reference design describes a scalable 10G Ethernet design with IEEE1588v2 feature enabled that demonstrates Ethernet operations of the Altera® Low Latency Ethernet 10G MAC and Arria 10 1G/10G Native PHY MegaCore® functions and 10GbaseR 1588 soft FIFO module targeted on Altera Arria 10 SI kit. It provides flexible test and demonstration platforms on which user can control, test, and monitor the Ethernet operations on the TX and RX data paths.|
|Development Kit||Arria 10 GX Transceiver Signal Integrity Development Kit|
Note: After downloading the design example, you must prepare the design template. The file you downloaded is of the form of a <project>.par file which contains a compressed version of your design files (similar to a .qar file) and metadata describing the project. The combination of this information is what constitutes a <project>.par file. In releases 16.0 or newer, you can simply double click on the <project>.par file and Quartus will launch that project.
Browse to the <project>.par file you downloaded, click next, followed by Finish, and your design template will be installed and displayed in the Project Navigator pane in Quartus.
Note: When a design is stored in the Design Store as a design template, it has been previously regression tested against the stated version of Quartus software. The regression ensures the design template passes analysis/synthesis/fitting/assembly steps in the Quartus design flow.
At the command-line, type the following command:
Once the process completes, then type:
|Total Downloads||68 (From 18 Nov 2016 to 12 Oct 2019)|
|Quartus Prime Version||Download Quartus Prime v16.0|
|Quartus Prime Edition||Standard|
Last updated on Jan. 19, 2017, 10:12 a.m.