Design Store

AN708: PCIe Gen3x8 AVMM DMA with External Memory  

CategoryDesign Example
NameAN708: PCIe Gen3x8 AVMM DMA with External Memory
DescriptionFeatures:
Fast and easy to develop high performance PCIe Gen3x8 hardware with PCIe AVMM DMA IP
Completed Quartus reference design is in the attached zipped file, which provides a pre-configured Qsys system
Allows the user to modify the Qsys file and re-generate the design
Includes Linux driver and application that works with the reference design
Use built in AVMM DMA IP to transfer data between the external DDR4 memory on the board and the system memory
Support infinite loop to test the system and the IP stability
For each loop, all transferred data are compared with data in the source location to guarantee data integrity

Requirements:
Quartus 16.0.2 (for RTL re-generation).
A PC provides a PCI Express Gen3 x8 slot
All reference designs have been tested with Intel Sandy Bridge
The attached reference design (The SOF is available in the folder pcie_quartus_files as top.sof)
Arria 10 GX FPGA Development Kit (Refer the link for Arria 10 FPGA development Kit : https://www.altera.com/products/boards_and_kits/dev-kits/altera/kit-a10-gx-fpga.html)
A system with either 32-bit / 64-bit Linux or 64-bit Windows installed
Operating SystemNone
IP Core
IP CoreHeading
JTAG Debug Link (internal module)ConfigurationProgramming
Avalon-ST Bytes to Packets ConverterQsysInterconnect
Avalon-ST Single Clock FIFOQsysInterconnect
Avalon-ST Timing AdapterQsysInterconnect
Avalon-ST JTAG InterfaceQsysInterconnect
Avalon-ST Packets to Bytes ConverterQsysInterconnect
Avalon MM Debug FabricQsysInterconnect
MM InterconnectQsysInterconnect
Avalon-ST Pipeline StageQsysInterconnect
Avalon-ST AdapterQsysInterconnect
Avalon-ST Error AdapterQsysInterconnect
Avalon-MM Slave AgentQsysInterconnect
Avalon-MM Slave TranslatorQsysInterconnect
Memory-Mapped DemultiplexerQsysInterconnect
Memory-Mapped MultiplexerQsysInterconnect
Memory-Mapped RouterQsysInterconnect
Avalon-MM Master AgentQsysInterconnect
Memory-Mapped Traffic LimiterQsysInterconnect
Avalon-MM Master TranslatorQsysInterconnect
Trace ROMQsysInterconnect
Avalon Packets to Transaction ConverterQsysInterconnect
Avalon ST Debug FabricQsysInterconnect
Avalon-ST DemultiplexerQsysInterconnect
Avalon-ST Dual Clock FIFOQsysInterconnect
Avalon-ST Channel AdapterQsysInterconnect
Altera Management Reset BlockOther
Reset ControllerQsysInterconnect
Avalon-ST MultiplexerQsysInterconnect
Arria 10 Hard IP for PCI ExpressPCIExpress
Arria 10 FPLLClocksPLLsResets
Arria 10 Transceiver ATX PLLTransceiverPLL
Arria 10 Transceiver Native PHYTransceiverPHY
Arria 10 External Memory InterfacesExternalMemoryInterfaces
EMIF Core Component for 20nm FamiliesExternalMemoryInterfaces
Arria 10 External Memory Interfaces Debug ComponentExternalMemoryInterfaces
Avalon-MM Pipeline BridgeQsysInterconnect
alt_mem_if JTAG to Avalon Master BridgeBridgesAndAdaptors
Arria 10 External Memory Interfaces IOAUX Master componentExternalMemoryInterfaces
On-Chip Memory (RAM or ROM)OnChipMemory
Avalon-MM Clock Crossing BridgeQsysInterconnect
Memory-Mapped Width AdapterQsysInterconnect
Memory-Mapped Burst AdapterQsysInterconnect
Version1.0
FamilyArria 10
Device10AX115
Documentation
DocumentDescription
Detailed Explanation-
Linux SoftwareFollow the following instructions to install and run the application: Copy the attached Linux application and driver into a folder Unzip the application and driver Open a Terminal in Linux and go to the folder where the application is copied and unzipped Log in as an Admin by type in "su" and enter the password Type in "make" to compile the driver and application. Just need to do it once in a system. Type in "./install" to install the driver Type in "./run" to run the application In the application, there are multiple options to configure the software. The user can run read DMA (move data from system memory to the DDR4 memory on the board), write DMA (move data from external DDR4 memory to system memory), or simultaneous read and write. The user can also control the transfer size of each descriptor, the number of descriptors, and how many loops the DMA runs. There are details to explain all the options when the application is started. To run the DMA, type in "1" to start it.
Windows Software64-bit Windows driver and application. In the package, there is a word document which explains how to install the driver, what additional software needs to be installed, and how to run the application.
Development KitArria 10 GX FPGA Development Kit
Installation Package

Note: After downloading the design example, you must prepare the design template. The file you downloaded is of the form of a <project>.par file which contains a compressed version of your design files (similar to a .qar file) and metadata describing the project. The combination of this information is what constitutes a <project>.par file. In releases 16.0 or newer, you can simply double click on the <project>.par file and Quartus will launch that project.

The second means to bring up the project template is through the New Project Wizard (File -> New Project Wizard). After entering the project name and folder on the first panel, the second panel will ask you to specify an empty project or project template. Select project template. You will see a list of Design Templates projects that you have loaded prior as well as various "Baseline Pinout Designs" that contain the pinout and settings for a variety of development kits. If you don't see your design template in the list, click on the link that states install the Design Templates circled below:


Browse to the <project>.par file you downloaded, click next, followed by Finish, and your design template will be installed and displayed in the Project Navigator pane in Quartus.

Note: When a design is stored in the Design Store as a design template, it has been previously regression tested against the stated version of Quartus software. The regression ensures the design template passes analysis/synthesis/fitting/assembly steps in the Quartus design flow.

At the command-line, type the following command:

quartus_sh --platform_install –package <project directory>/hip_a10gx_g3_x8_avmm_dma256_1602.par

Once the process completes, then type:

quartus_sh --platform –name hip_a10gx_g3_x8_avmm_dma256_1602

Download
Total Downloads111 (From 18 Jul 2017 to 19 Aug 2019)
Quartus Prime VersionDownload Quartus Prime v16.0
Quartus Prime EditionStandard
VendorIntel


Last updated on June 22, 2018, 2:11 a.m.